Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51230 )
Change subject: arch-sparc: Implement RegClass based register flattening.
......................................................................
arch-sparc: Implement RegClass based register flattening.
Change-Id: Ib1d5b7ac7ff5aa6f35099fd9fd4530951c3efa19
---
M src/arch/sparc/SConscript
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
A src/arch/sparc/regs/int.cc
M src/arch/sparc/regs/int.hh
5 files changed, 73 insertions(+), 3 deletions(-)
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index d17caa9..4212388 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -39,6 +39,7 @@
Source('nativetrace.cc')
Source('pagetable.cc')
Source('process.cc')
+ Source('regs/int.cc')
Source('remote_gdb.cc')
Source('se_workload.cc')
Source('tlb.cc')
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index f940424..a29d1b9 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -79,7 +79,7 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&flatIntRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index fc5963c..6be7ba7 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -167,6 +167,7 @@
void reloadRegMap();
public:
+ const RegIndex &mapIntRegId(RegIndex idx) const { return
intRegMap[idx]; }
void clear();
diff --git a/src/arch/sparc/regs/int.cc b/src/arch/sparc/regs/int.cc
new file mode 100644
index 0000000..47f0507
--- /dev/null
+++ b/src/arch/sparc/regs/int.cc
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/sparc/regs/int.hh"
+
+#include "arch/sparc/isa.hh"
+
+namespace gem5
+{
+
+namespace SparcISA
+{
+
+RegId
+IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
+{
+ auto &sparc_isa = static_cast<const SparcISA::ISA &>(isa);
+ return {flatIntRegClass, sparc_isa.mapIntRegId(id.index())};
+}
+
+} // namespace SparcISA
+} // namespace gem5
diff --git a/src/arch/sparc/regs/int.hh b/src/arch/sparc/regs/int.hh
index 9cc2b2e..faa9542 100644
--- a/src/arch/sparc/regs/int.hh
+++ b/src/arch/sparc/regs/int.hh
@@ -68,8 +68,20 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
- debug::IntRegs);
+class IntRegClassOps : public RegClassOps
+{
+ RegId flatten(const BaseISA &isa, const RegId &id) const override;
+};
+
+inline constexpr IntRegClassOps intRegClassOps;
+
+inline constexpr RegClass intRegClass =
+ RegClass(IntRegClass, "integer", int_reg::NumRegs, debug::IntRegs).
+ ops(intRegClassOps).
+ needsFlattening();
+
+inline constexpr RegClass flatIntRegClass =
+ RegClass(IntRegClass, "integer", int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib1d5b7ac7ff5aa6f35099fd9fd4530951c3efa19
Gerrit-Change-Number: 51230
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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