Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51229 )
Change subject: arch-arm: Implement RegClass based register flattening.
......................................................................
arch-arm: Implement RegClass based register flattening.
Change-Id: Iba5c74d5b6dccd7de3ff59fea18a0c27c74c56a3
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
A src/arch/arm/regs/int.cc
M src/arch/arm/regs/int.hh
M src/arch/arm/SConscript
5 files changed, 122 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index ac004dd..d1bae5f 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -79,6 +79,7 @@
Source('freebsd/fs_workload.cc')
Source('freebsd/se_workload.cc')
Source('fs_workload.cc')
+ Source('regs/int.cc')
Source('regs/misc.cc')
Source('mmu.cc')
Source('nativetrace.cc')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8b3cf82..d2b4f8b 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -81,7 +81,7 @@
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
- _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&flatIntRegClass);
_regClasses.push_back(&floatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8b7b790..c8d7a7a 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -450,6 +450,9 @@
void initializeMiscRegMetadata();
+ BaseISADevice &getGenericTimer();
+ BaseISADevice &getGICv3CPUInterface();
+
RegVal miscRegs[NUM_MISCREGS];
const RegId *intRegMap;
@@ -491,8 +494,8 @@
}
}
- BaseISADevice &getGenericTimer();
- BaseISADevice &getGICv3CPUInterface();
+ public:
+ const RegId &mapIntRegId(RegIndex idx) const { return
intRegMap[idx]; }
private:
void assert32() { assert(((CPSR)readMiscReg(MISCREG_CPSR)).width);
}
diff --git a/src/arch/arm/regs/int.cc b/src/arch/arm/regs/int.cc
new file mode 100644
index 0000000..d1a7edd
--- /dev/null
+++ b/src/arch/arm/regs/int.cc
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2010-2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/arm/regs/int.hh"
+
+#include "arch/arm/isa.hh"
+#include "arch/arm/regs/misc.hh"
+#include "arch/arm/utility.hh"
+#include "base/logging.hh"
+
+namespace gem5
+{
+
+namespace ArmISA
+{
+
+RegId
+IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
+{
+ const RegIndex reg_idx = id.index();
+
+ auto &arm_isa = static_cast<const ArmISA::ISA &>(isa);
+
+ if (reg_idx < int_reg::NumArchRegs) {
+ return {flatIntRegClass, arm_isa.mapIntRegId(reg_idx)};
+ } else if (reg_idx < int_reg::NumRegs) {
+ return {flatIntRegClass, id};
+ } else if (reg_idx == int_reg::Spx) {
+ auto &arm_isa = static_cast<const ArmISA::ISA &>(isa);
+ CPSR cpsr = arm_isa.readMiscRegNoEffect(MISCREG_CPSR);
+ ExceptionLevel el = opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
+
+ if (!cpsr.sp && el != EL0)
+ return {flatIntRegClass, int_reg::Sp0};
+
+ switch (el) {
+ case EL3:
+ return {flatIntRegClass, int_reg::Sp3};
+ case EL2:
+ return {flatIntRegClass, int_reg::Sp2};
+ case EL1:
+ return {flatIntRegClass, int_reg::Sp1};
+ case EL0:
+ return {flatIntRegClass, int_reg::Sp0};
+ default:
+ panic("Invalid exception level");
+ }
+ } else {
+ return {flatIntRegClass, flattenIntRegModeIndex(reg_idx)};
+ }
+}
+
+} // namespace ArmISA
+} // namespace gem5
diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh
index 8c8d591..986f131 100644
--- a/src/arch/arm/regs/int.hh
+++ b/src/arch/arm/regs/int.hh
@@ -163,8 +163,20 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
- debug::IntRegs);
+class IntRegClassOps : public RegClassOps
+{
+ RegId flatten(const BaseISA &isa, const RegId &id) const override;
+};
+
+inline constexpr IntRegClassOps intRegClassOps;
+
+inline constexpr RegClass intRegClass =
+ RegClass(IntRegClass, "integer", int_reg::NumRegs, debug::IntRegs).
+ ops(intRegClassOps).
+ needsFlattening();
+
+inline constexpr RegClass flatIntRegClass =
+ RegClass(IntRegClass, "integer", int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{
@@ -559,7 +571,7 @@
} // namespace int_reg
-static inline int
+static inline const RegId &
flattenIntRegModeIndex(int reg)
{
int mode = reg / int_reg::regsPerMode;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51229
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iba5c74d5b6dccd7de3ff59fea18a0c27c74c56a3
Gerrit-Change-Number: 51229
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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