Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51231 )
Change subject: arch,cpu: Replace calls to (get|set)RegFlat.
......................................................................
arch,cpu: Replace calls to (get|set)RegFlat.
Make these use RegIds which are based on already flattened RegClass-es.
Change-Id: I50f50614830c7010c18a8ebb95aba8decc078ac0
---
M src/cpu/o3/thread_context.cc
M src/cpu/o3/thread_context.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/cpu/o3/cpu.cc
M src/arch/arm/kvm/armv8_cpu.cc
M src/arch/arm/isa.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/x86/isa.cc
M src/arch/mips/isa.cc
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
12 files changed, 102 insertions(+), 111 deletions(-)
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index 98f0416..a27960e 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -622,52 +622,23 @@
RegVal
ThreadContext::getReg(const RegId ®) const
{
- return getRegFlat(flattenRegId(reg));
+ RegVal val;
+ getReg(reg, &val);
+ return val;
}
void
ThreadContext::setReg(const RegId ®, RegVal val)
{
- setRegFlat(flattenRegId(reg), val);
+ setReg(reg, &val);
}
void
ThreadContext::getReg(const RegId ®, void *val) const
{
- getRegFlat(flattenRegId(reg), val);
-}
-
-void
-ThreadContext::setReg(const RegId ®, const void *val)
-{
- setRegFlat(flattenRegId(reg), val);
-}
-
-void *
-ThreadContext::getWritableReg(const RegId ®)
-{
- return getWritableRegFlat(flattenRegId(reg));
-}
-
-RegVal
-ThreadContext::getRegFlat(const RegId ®) const
-{
- RegVal val;
- getRegFlat(reg, &val);
- return val;
-}
-
-void
-ThreadContext::setRegFlat(const RegId ®, RegVal val)
-{
- setRegFlat(reg, &val);
-}
-
-void
-ThreadContext::getRegFlat(const RegId ®, void *val) const
-{
- const RegIndex idx = reg.index();
- const RegClassType type = reg.classValue();
+ const RegId flat = reg.flatten(*_isa);
+ const RegIndex idx = flat.index();
+ const RegClassType type = flat.classValue();
switch (type) {
case IntRegClass:
*(RegVal *)val = readIntRegFlat(idx);
@@ -692,10 +663,11 @@
}
void
-ThreadContext::setRegFlat(const RegId ®, const void *val)
+ThreadContext::setReg(const RegId ®, const void *val)
{
- const RegIndex idx = reg.index();
- const RegClassType type = reg.classValue();
+ const RegId flat = reg.flatten(*_isa);
+ const RegIndex idx = flat.index();
+ const RegClassType type = flat.classValue();
switch (type) {
case IntRegClass:
setIntRegFlat(idx, *(RegVal *)val);
@@ -720,10 +692,11 @@
}
void *
-ThreadContext::getRegWritableFlat(const RegId ®)
+ThreadContext::getRegWritable(const RegId ®)
{
- const RegIndex idx = reg.index();
- const RegClassType type = reg.classValue();
+ const RegId flat = reg.flatten(*_isa);
+ const RegIndex idx = flat.index();
+ const RegClassType type = flat.classValue();
switch (type) {
case VecRegClass:
return &getWritableVecRegFlat(idx);
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index 746afe1..05e06e3 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -394,12 +394,12 @@
* serialization code to access all registers.
*/
- RegVal getRegFlat(const RegId ®) const override;
- void getRegFlat(const RegId ®, void *val) const override;
- void *getWritableRegFlat(const RegId ®) override;
+ RegVal getReg(const RegId ®) const override;
+ void getReg(const RegId ®, void *val) const override;
+ void *getWritableReg(const RegId ®) override;
- void setRegFlat(const RegId ®, RegVal val) override;
- void setRegFlat(const RegId ®, const void *val) override;
+ void setReg(const RegId ®, RegVal val) override;
+ void setReg(const RegId ®, const void *val) override;
virtual RegVal readIntRegFlat(RegIndex idx) const;
virtual void setIntRegFlat(RegIndex idx, uint64_t val);
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d2b4f8b..681bc53 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -549,8 +549,8 @@
void
ISA::copyRegsFrom(ThreadContext *src)
{
- for (auto &id: intRegClass)
- tc->setRegFlat(id, src->getRegFlat(id));
+ for (auto &id: flatIntRegClass)
+ tc->setReg(id, src->getReg(id));
for (auto &id: ccRegClass)
tc->setReg(id, src->getReg(id));
@@ -560,12 +560,12 @@
ArmISA::VecRegContainer vc;
for (auto &id: vecRegClass) {
- src->getRegFlat(id, &vc);
- tc->setRegFlat(id, &vc);
+ src->getReg(id, &vc);
+ tc->setReg(id, &vc);
}
for (auto &id: vecElemClass)
- tc->setRegFlat(id, src->getRegFlat(id));
+ tc->setReg(id, src->getReg(id));
// setMiscReg "with effect" will set the misc register mapping
correctly.
// e.g. updateRegMap(val)
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 5183b0f..a7d9f52 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -663,7 +663,7 @@
for (const KvmIntRegInfo *ri(kvmIntRegs);
ri->idx != init_reg::NumRegs; ++ri) {
- uint64_t value = tc->getRegFlat(intRegClass[ri->idx]);
+ uint64_t value = tc->getReg(flatIntRegClass[ri->idx]);
DPRINTF(KvmContext, "kvm(%s) := 0x%x\n", ri->name, value);
setOneReg(ri->id, value);
}
@@ -771,8 +771,8 @@
const unsigned idx_base = idx << 1;
const unsigned idx_hi = idx_base + 1;
const unsigned idx_lo = idx_base + 0;
- uint64_t value = (tc->getRegFlat(floatRegClass[idx_hi]) << 32) |
- tc->getRegFlat(floatRegClass[idx_lo]);
+ uint64_t value = (tc->getReg(floatRegClass[idx_hi]) << 32) |
+ tc->getReg(floatRegClass[idx_lo]);
setOneReg(id, value);
} else if (regIsVfpCtrl(id)) {
@@ -802,7 +802,7 @@
for (const KvmIntRegInfo *ri(kvmIntRegs);
ri->idx != int_reg::NumRegs; ++ri) {
- tc->setRegFlat(intRegClass[ri->idx], getOneRegU32(ri->id));
+ tc->setReg(intRegClass[ri->idx], getOneRegU32(ri->id));
}
for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs);
@@ -913,8 +913,8 @@
const unsigned idx_lo = idx_base + 0;
uint64_t value = getOneRegU64(id);
- tc->setRegFlat(floatRegClass[idx_hi], (value >> 32) & 0xFFFFFFFF);
- tc->setRegFlat(floatRegClass[idx_lo], value & 0xFFFFFFFF);
+ tc->setReg(floatRegClass[idx_hi], (value >> 32) & 0xFFFFFFFF);
+ tc->setReg(floatRegClass[idx_lo], value & 0xFFFFFFFF);
} else if (regIsVfpCtrl(id)) {
MiscRegIndex idx = decodeVFPCtrlReg(id);
if (idx == NUM_MISCREGS) {
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 7b81265..e3ea7d4 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -322,7 +322,7 @@
if (inAArch64(tc)) {
tc->setReg(int_reg::x(i), value);
} else {
- tc->setRegFlat(int_reg::x(i), value);
+ tc->setReg(flatIntRegClass[i], value);
}
}
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index f19f904..86f19c0 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -185,11 +185,11 @@
{
// First loop through the integer registers.
for (auto &id: intRegClass)
- tc->setRegFlat(id, src->getRegFlat(id));
+ tc->setReg(id, src->getReg(id));
// Then loop through the floating point registers.
for (auto &id: floatRegClass)
- tc->setRegFlat(id, src->getRegFlat(id));
+ tc->setReg(id, src->getReg(id));
// Copy misc. registers
for (int i = 0; i < misc_reg::NumRegs; i++)
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 4487441..d5d92de 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -189,14 +189,14 @@
ISA::copyRegsFrom(ThreadContext *src)
{
//copy int regs
- for (auto &id: intRegClass)
- tc->setRegFlat(id, tc->getRegFlat(id));
+ for (auto &id: flatIntRegClass)
+ tc->setReg(id, tc->getReg(id));
//copy float regs
- for (auto &id: floatRegClass)
- tc->setRegFlat(id, src->getRegFlat(id));
+ for (auto &id: flatFloatRegClass)
+ tc->setReg(id, src->getReg(id));
//copy condition-code regs
for (auto &id: ccRegClass)
- tc->setRegFlat(id, src->getRegFlat(id));
+ tc->setReg(id, src->getReg(id));
copyMiscRegs(src, tc);
tc->pcState(src->pcState());
}
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 53fd9d4..41c520a 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1087,7 +1087,8 @@
default:
break;
}
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ const RegId flat = reg.flatten(*isa[tid]);
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(flat);
return getReg(phys_reg);
}
@@ -1114,7 +1115,8 @@
default:
break;
}
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ const RegId flat = reg.flatten(*isa[tid]);
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(flat);
getReg(phys_reg, val);
}
@@ -1131,7 +1133,8 @@
default:
break;
}
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ const RegId flat = reg.flatten(*isa[tid]);
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(flat);
return getWritableReg(phys_reg);
}
@@ -1158,7 +1161,8 @@
default:
break;
}
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ const RegId flat = reg.flatten(*isa[tid]);
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(flat);
setReg(phys_reg, val);
}
@@ -1185,7 +1189,8 @@
default:
break;
}
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(reg);
+ const RegId flat = reg.flatten(*isa[tid]);
+ PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(flat);
setReg(phys_reg, val);
}
diff --git a/src/cpu/o3/thread_context.cc b/src/cpu/o3/thread_context.cc
index 36dff1e..836dd53 100644
--- a/src/cpu/o3/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -149,32 +149,32 @@
}
RegVal
-ThreadContext::getRegFlat(const RegId ®) const
+ThreadContext::getReg(const RegId ®) const
{
return cpu->getArchReg(reg, thread->threadId());
}
void *
-ThreadContext::getWritableRegFlat(const RegId ®)
+ThreadContext::getWritableReg(const RegId ®)
{
return cpu->getWritableArchReg(reg, thread->threadId());
}
void
-ThreadContext::getRegFlat(const RegId ®, void *val) const
+ThreadContext::getReg(const RegId ®, void *val) const
{
cpu->getArchReg(reg, val, thread->threadId());
}
void
-ThreadContext::setRegFlat(const RegId ®, RegVal val)
+ThreadContext::setReg(const RegId ®, RegVal val)
{
cpu->setArchReg(reg, val, thread->threadId());
conditionalSquash();
}
void
-ThreadContext::setRegFlat(const RegId ®, const void *val)
+ThreadContext::setReg(const RegId ®, const void *val)
{
cpu->setArchReg(reg, val, thread->threadId());
conditionalSquash();
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index a30579c..2876f7f 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -260,12 +260,12 @@
cpu->squashFromTC(thread->threadId());
}
- RegVal getRegFlat(const RegId ®) const override;
- void getRegFlat(const RegId ®, void *val) const override;
- void *getWritableRegFlat(const RegId ®) override;
+ RegVal getReg(const RegId ®) const override;
+ void getReg(const RegId ®, void *val) const override;
+ void *getWritableReg(const RegId ®) override;
- void setRegFlat(const RegId ®, RegVal val) override;
- void setRegFlat(const RegId ®, const void *val) override;
+ void setReg(const RegId ®, RegVal val) override;
+ void setReg(const RegId ®, const void *val) override;
// hardware transactional memory
void htmAbortTransaction(uint64_t htm_uid,
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index b3359a4..e0ebaf3 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -166,45 +166,47 @@
RegVal
ThreadContext::getReg(const RegId ®) const
{
- return getRegFlat(flattenRegId(reg));
-}
-
-void *
-ThreadContext::getWritableReg(const RegId ®)
-{
- return getWritableRegFlat(flattenRegId(reg));
+ RegVal val;
+ getReg(reg, &val);
+ return val;
}
void
ThreadContext::setReg(const RegId ®, RegVal val)
{
- setRegFlat(flattenRegId(reg), val);
-}
-
-void
-ThreadContext::getReg(const RegId ®, void *val) const
-{
- getRegFlat(flattenRegId(reg), val);
-}
-
-void
-ThreadContext::setReg(const RegId ®, const void *val)
-{
- setRegFlat(flattenRegId(reg), val);
+ setReg(reg, &val);
}
RegVal
ThreadContext::getRegFlat(const RegId ®) const
{
RegVal val;
- getRegFlat(reg, &val);
+ getReg(reg, &val);
return val;
}
void
+ThreadContext::getRegFlat(const RegId ®, void *val) const
+{
+ getReg(reg, val);
+}
+
+void *
+ThreadContext::getWritableRegFlat(const RegId ®)
+{
+ return getWritableReg(reg);
+}
+
+void
ThreadContext::setRegFlat(const RegId ®, RegVal val)
{
- setRegFlat(reg, &val);
+ setReg(reg, &val);
+}
+
+void
+ThreadContext::setRegFlat(const RegId ®, const void *val)
+{
+ setReg(reg, val);
}
void
@@ -221,7 +223,7 @@
uint8_t regs[reg_count * reg_bytes];
auto *reg_ptr = regs;
for (const auto &id: *reg_class) {
- tc.getRegFlat(id, reg_ptr);
+ tc.getReg(id, reg_ptr);
reg_ptr += reg_bytes;
}
@@ -251,7 +253,7 @@
auto *reg_ptr = regs;
for (const auto &id: *reg_class) {
- tc.setRegFlat(id, reg_ptr);
+ tc.setReg(id, reg_ptr);
reg_ptr += reg_bytes;
}
}
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 5a7fed0..04c658d 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -192,11 +192,11 @@
// New accessors for new decoder.
//
virtual RegVal getReg(const RegId ®) const;
- virtual void getReg(const RegId ®, void *val) const;
- virtual void *getWritableReg(const RegId ®);
+ virtual void getReg(const RegId ®, void *val) const = 0;
+ virtual void *getWritableReg(const RegId ®) = 0;
virtual void setReg(const RegId ®, RegVal val);
- virtual void setReg(const RegId ®, const void *val);
+ virtual void setReg(const RegId ®, const void *val) = 0;
virtual TheISA::PCState pcState() const = 0;
@@ -255,11 +255,11 @@
*/
virtual RegVal getRegFlat(const RegId ®) const;
- virtual void getRegFlat(const RegId ®, void *val) const = 0;
- virtual void *getWritableRegFlat(const RegId ®) = 0;
+ virtual void getRegFlat(const RegId ®, void *val) const;
+ virtual void *getWritableRegFlat(const RegId ®);
virtual void setRegFlat(const RegId ®, RegVal val);
- virtual void setRegFlat(const RegId ®, const void *val) = 0;
+ virtual void setRegFlat(const RegId ®, const void *val);
/** @} */
// hardware transactional memory
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51231
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I50f50614830c7010c18a8ebb95aba8decc078ac0
Gerrit-Change-Number: 51231
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
