Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51228 )
Change subject: arch-x86: Implement RegClass flattening.
......................................................................
arch-x86: Implement RegClass flattening.
This implements flattening in the x86 integer and floating point
RegClass-es, as well as adding regName functions for each. These came
from the X86StaticInst::printReg function, and the flattening functions
in the X86ISA::ISA class.
Change-Id: If026e3b44aa64441222451d91e99778f6054d9f0
---
A src/arch/x86/regs/float.cc
M src/arch/x86/regs/float.hh
M src/arch/x86/regs/SConscript
M src/arch/x86/isa.cc
A src/arch/x86/regs/int.cc
M src/arch/x86/regs/int.hh
6 files changed, 302 insertions(+), 12 deletions(-)
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 18e0ddf6..4487441 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -154,8 +154,8 @@
fatal_if(vendorString.size() != 12,
"CPUID vendor string must be 12 characters\n");
- _regClasses.push_back(&intRegClass);
- _regClasses.push_back(&floatRegClass);
+ _regClasses.push_back(&flatIntRegClass);
+ _regClasses.push_back(&flatFloatRegClass);
_regClasses.push_back(&vecRegClass);
_regClasses.push_back(&vecElemClass);
_regClasses.push_back(&vecPredRegClass);
diff --git a/src/arch/x86/regs/SConscript b/src/arch/x86/regs/SConscript
index a21e06a..90a07e9 100644
--- a/src/arch/x86/regs/SConscript
+++ b/src/arch/x86/regs/SConscript
@@ -29,4 +29,6 @@
Import('*')
if env['TARGET_ISA'] == 'x86':
+ Source('float.cc')
+ Source('int.cc')
Source('msr.cc')
diff --git a/src/arch/x86/regs/float.cc b/src/arch/x86/regs/float.cc
new file mode 100644
index 0000000..44bb774
--- /dev/null
+++ b/src/arch/x86/regs/float.cc
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sstream>
+
+#include "arch/x86/isa.hh"
+#include "arch/x86/regs/misc.hh"
+
+namespace gem5
+{
+namespace X86ISA
+{
+
+std::string
+FlatFloatRegClassOps::regName(const RegId &id) const
+{
+ std::ostringstream ss;
+
+ RegIndex reg_idx = id.index();
+
+ if (reg_idx < NumMMXRegs) {
+ ccprintf(ss, "%%mmx%d", reg_idx);
+ return ss.str();
+ }
+ reg_idx -= NumMMXRegs;
+ if (reg_idx < NumXMMRegs * 2) {
+ ccprintf(ss, "%%xmm%d_%s", reg_idx / 2,
+ (reg_idx % 2) ? "high": "low");
+ return ss.str();
+ }
+ reg_idx -= NumXMMRegs * 2;
+ if (reg_idx < NumMicroFpRegs) {
+ ccprintf(ss, "%%ufp%d", reg_idx);
+ return ss.str();
+ }
+ reg_idx -= NumMicroFpRegs;
+ ccprintf(ss, "%%st(%d)", reg_idx);
+
+ return ss.str();
+}
+
+RegId
+FloatRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
+{
+ RegIndex idx = id.index();
+
+ if (idx >= float_reg::NumRegs) {
+ auto &x86_isa = static_cast<const X86ISA::ISA &>(isa);
+ auto x87_top = x86_isa.readMiscRegNoEffect(misc_reg::X87Top);
+ idx = float_reg::stack(idx - float_reg::NumRegs, x87_top);
+ }
+
+ return {flatFloatRegClass, idx};
+}
+
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index 30c3e17..894add1 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -35,8 +35,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __ARCH_X86_FLOATREGS_HH__
-#define __ARCH_X86_FLOATREGS_HH__
+#ifndef __ARCH_X86_REGS_FLOAT_HH__
+#define __ARCH_X86_REGS_FLOAT_HH__
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
@@ -121,8 +121,30 @@
} // namespace float_reg
-inline constexpr RegClass floatRegClass(FloatRegClass, "floating_point",
- float_reg::NumRegs, debug::FloatRegs);
+class FlatFloatRegClassOps : public RegClassOps
+{
+ std::string regName(const RegId &id) const override;
+};
+
+inline constexpr FlatFloatRegClassOps flatFloatRegClassOps;
+
+inline constexpr RegClass flatFloatRegClass =
+ RegClass(FloatRegClass, "floating_point", float_reg::NumRegs,
+ debug::FloatRegs).
+ ops(flatFloatRegClassOps);
+
+class FloatRegClassOps : public FlatFloatRegClassOps
+{
+ RegId flatten(const BaseISA &isa, const RegId &id) const override;
+};
+
+inline constexpr FloatRegClassOps floatRegClassOps;
+
+inline constexpr RegClass floatRegClass =
+ RegClass(FloatRegClass, "floating_point", float_reg::NumRegs,
+ debug::FloatRegs).
+ ops(floatRegClassOps).
+ needsFlattening();
namespace float_reg
{
@@ -174,4 +196,4 @@
} // namespace X86ISA
} // namespace gem5
-#endif // __ARCH_X86_FLOATREGS_HH__
+#endif // __ARCH_X86_REGS_FLOAT_HH__
diff --git a/src/arch/x86/regs/int.cc b/src/arch/x86/regs/int.cc
new file mode 100644
index 0000000..fa09c41
--- /dev/null
+++ b/src/arch/x86/regs/int.cc
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/x86/regs/int.hh"
+
+#include <sstream>
+
+namespace gem5
+{
+
+namespace X86ISA
+{
+
+std::string
+FlatIntRegClassOps::regName(const RegId &id) const
+{
+ constexpr const char *abcdFormats[9] =
+ {"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
+ constexpr const char *piFormats[9] =
+ {"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
+ constexpr const char *longFormats[9] =
+ {"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
+ constexpr const char *microFormats[9] =
+ {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
+
+ // Fix size at 8 for now.
+ constexpr unsigned size = 8;
+
+ RegIndex reg_idx = id.index();
+
+ std::ostringstream ss;
+
+ const char * suffix = "";
+ bool fold = reg_idx & IntFoldBit;
+ reg_idx &= ~IntFoldBit;
+
+ if (fold)
+ suffix = "h";
+ else if (reg_idx < 8 && size == 1)
+ suffix = "l";
+
+ switch (reg_idx) {
+ case int_reg::Rax:
+ ccprintf(ss, abcdFormats[size], "a");
+ break;
+ case int_reg::Rbx:
+ ccprintf(ss, abcdFormats[size], "b");
+ break;
+ case int_reg::Rcx:
+ ccprintf(ss, abcdFormats[size], "c");
+ break;
+ case int_reg::Rdx:
+ ccprintf(ss, abcdFormats[size], "d");
+ break;
+ case int_reg::Rsp:
+ ccprintf(ss, piFormats[size], "sp");
+ break;
+ case int_reg::Rbp:
+ ccprintf(ss, piFormats[size], "bp");
+ break;
+ case int_reg::Rsi:
+ ccprintf(ss, piFormats[size], "si");
+ break;
+ case int_reg::Rdi:
+ ccprintf(ss, piFormats[size], "di");
+ break;
+ case int_reg::R8:
+ ccprintf(ss, longFormats[size], "8");
+ break;
+ case int_reg::R9:
+ ccprintf(ss, longFormats[size], "9");
+ break;
+ case int_reg::R10:
+ ccprintf(ss, longFormats[size], "10");
+ break;
+ case int_reg::R11:
+ ccprintf(ss, longFormats[size], "11");
+ break;
+ case int_reg::R12:
+ ccprintf(ss, longFormats[size], "12");
+ break;
+ case int_reg::R13:
+ ccprintf(ss, longFormats[size], "13");
+ break;
+ case int_reg::R14:
+ ccprintf(ss, longFormats[size], "14");
+ break;
+ case int_reg::R15:
+ ccprintf(ss, longFormats[size], "15");
+ break;
+ default:
+ ccprintf(ss, microFormats[size],
+ reg_idx - int_reg::MicroBegin);
+ }
+ ccprintf(ss, suffix);
+
+ return ss.str();
+}
+
+RegId
+IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
+{
+ return {flatIntRegClass, (RegIndex)(id.index() & ~IntFoldBit)};
+}
+
+} // namespace X86ISA
+} // namespace gem5
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index 56ac923..8d0e4ab 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -35,8 +35,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __ARCH_X86_INTREGS_HH__
-#define __ARCH_X86_INTREGS_HH__
+#ifndef __ARCH_X86_REGS_INT_HH__
+#define __ARCH_X86_REGS_INT_HH__
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
@@ -102,8 +102,28 @@
} // namespace int_reg
-inline constexpr RegClass intRegClass(IntRegClass, "integer",
int_reg::NumRegs,
- debug::IntRegs);
+class FlatIntRegClassOps : public RegClassOps
+{
+ std::string regName(const RegId &id) const override;
+};
+
+inline constexpr FlatIntRegClassOps flatIntRegClassOps;
+
+inline constexpr RegClass flatIntRegClass =
+ RegClass(IntRegClass, "integer", int_reg::NumRegs, debug::IntRegs).
+ ops(flatIntRegClassOps);
+
+class IntRegClassOps : public FlatIntRegClassOps
+{
+ RegId flatten(const BaseISA &isa, const RegId &id) const override;
+};
+
+inline constexpr IntRegClassOps intRegClassOps;
+
+inline constexpr RegClass intRegClass =
+ RegClass(IntRegClass, "integer", int_reg::NumRegs, debug::IntRegs).
+ ops(intRegClassOps).
+ needsFlattening();
namespace int_reg
{
@@ -174,4 +194,4 @@
} // namespace X86ISA
} // namespace gem5
-#endif // __ARCH_X86_INTREGS_HH__
+#endif // __ARCH_X86_REGS_INT_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51228
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If026e3b44aa64441222451d91e99778f6054d9f0
Gerrit-Change-Number: 51228
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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