Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51233 )
Change subject: arch-arm,cpu: Remove all uses of flattenRegId.
......................................................................
arch-arm,cpu: Remove all uses of flattenRegId.
RegIds can now be flattened directly.
Change-Id: I2a603c12bbc586720082363996f303cd3b43ac9c
---
M src/cpu/simple_thread.hh
M src/arch/arm/isa/insts/fp.isa
M src/cpu/o3/rename.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/insts/data64.isa
M src/cpu/minor/scoreboard.cc
6 files changed, 54 insertions(+), 48 deletions(-)
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 6e0847f..456979a 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -323,8 +323,8 @@
msr_check_code = '''
auto pre_flat = (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase());
- MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
- flattenRegId(miscRegClass[pre_flat]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto flat_idx = (MiscRegIndex)isa->flattenMiscIndex(pre_flat);
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
@@ -332,8 +332,8 @@
mrs_check_code = '''
auto pre_flat = (MiscRegIndex)snsBankedIndex64(op1, xc->tcBase());
- MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
- flattenRegId(miscRegClass[pre_flat]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto flat_idx = (MiscRegIndex)isa->flattenMiscIndex(pre_flat);
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
@@ -516,8 +516,8 @@
msrImmPermission = '''
auto pre_flat =
(MiscRegIndex)snsBankedIndex64(dest, xc->tcBase());
- MiscRegIndex misc_index = (MiscRegIndex) xc->tcBase()->
- flattenRegId(miscRegClass[pre_flat]).index();
+ auto *isa = static_cast<ArmISA::ISA
*>(xc->tcBase()->getIsaPtr());
+ auto misc_index =
(MiscRegIndex)isa->flattenMiscIndex(pre_flat);
if (!miscRegInfo[misc_index][MISCREG_IMPLEMENTED]) {
return std::make_shared<UndefinedInstruction>(
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 43a3214..47af309 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -213,7 +213,7 @@
if (!isSecure(xc->tcBase()) && (cpsr.mode != MODE_HYP)) {
HCR hcr = Hcr;
bool hypTrap = false;
- switch (xc->tcBase()->flattenRegId(miscRegClass[op1]).index()) {
+ switch (miscRegClass[op1].flatten(*xc->tcBase()->getIsaPtr())) {
case MISCREG_FPSID:
hypTrap = hcr.tid0;
break;
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index f59d714..4f99675 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -889,8 +889,8 @@
exec_output += PredOpExecute.subst(bfiIop)
mrc14code = '''
- MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
- miscRegClass[op1]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(op1);
auto [can_read, undefined] = canReadCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
if (!can_read || undefined) {
@@ -914,8 +914,8 @@
mcr14code = '''
- MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
- miscRegClass[dest]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(dest);
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
if (undefined || !can_write) {
@@ -939,9 +939,8 @@
mrc15code = '''
int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
- MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenRegId(miscRegClass[
- preFlatOp1]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatOp1);
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
@@ -971,9 +970,8 @@
mcr15code = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
- MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenRegId(miscRegClass[
- preFlatDest]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatDest);
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
@@ -1004,9 +1002,8 @@
mrrc15code = '''
int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
- MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenRegId(miscRegClass[
- preFlatOp1]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatOp1);
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
@@ -1036,9 +1033,8 @@
mcrr15code = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
- MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenRegId(miscRegClass[
-
preFlatDest]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatDest);
Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
@@ -1114,8 +1110,8 @@
McrDcCheckCode = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
- MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
- miscRegClass[preFlatDest]).index();
+ auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
+ auto miscReg = (MiscRegIndex)isa->flattenMiscIndex(preFlatDest);
bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index 926d01d..2bb6966 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -89,13 +89,6 @@
return ret;
}
-/** Flatten a RegId, irrespective of what reg type it's pointing to */
-static RegId
-flattenRegIndex(const RegId& reg, ThreadContext *thread_context)
-{
- return thread_context->flattenRegId(reg);
-}
-
void
Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
ThreadContext *thread_context, bool mark_unpredictable)
@@ -106,12 +99,13 @@
StaticInstPtr staticInst = inst->staticInst;
unsigned int num_dests = staticInst->numDestRegs();
+ auto *isa = thread_context->getIsaPtr();
+
/** Mark each destination register */
for (unsigned int dest_index = 0; dest_index < num_dests;
dest_index++)
{
- RegId reg = flattenRegIndex(
- staticInst->destRegIdx(dest_index), thread_context);
+ RegId reg = staticInst->destRegIdx(dest_index).flatten(*isa);
Index index;
if (findIndex(reg, index)) {
@@ -151,9 +145,10 @@
StaticInstPtr staticInst = inst->staticInst;
unsigned int num_srcs = staticInst->numSrcRegs();
+ auto *isa = thread_context->getIsaPtr();
+
for (unsigned int src_index = 0; src_index < num_srcs; src_index++) {
- RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
- thread_context);
+ RegId reg = staticInst->srcRegIdx(src_index).flatten(*isa);
unsigned short int index;
if (findIndex(reg, index)) {
@@ -233,13 +228,14 @@
[num_relative_latencies-1];
}
+ auto *isa = thread_context->getIsaPtr();
+
/* For each source register, find the latest result */
unsigned int src_index = 0;
while (src_index < num_srcs && /* More registers */
ret /* Still possible */)
{
- RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
- thread_context);
+ RegId reg = staticInst->srcRegIdx(src_index).flatten(*isa);
unsigned short int index;
if (findIndex(reg, index)) {
diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc
index 3f3afec..80e73dd 100644
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -1007,15 +1007,17 @@
gem5::ThreadContext *tc = inst->tcBase();
UnifiedRenameMap *map = renameMap[tid];
unsigned num_src_regs = inst->numSrcRegs();
+ auto *isa = tc->getIsaPtr();
// Get the architectual register numbers from the source and
// operands, and redirect them to the right physical register.
for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
const RegId& src_reg = inst->srcRegIdx(src_idx);
+ const RegId flat_reg = src_reg.flatten(*isa);
PhysRegIdPtr renamed_reg;
- renamed_reg = map->lookup(tc->flattenRegId(src_reg));
- switch (src_reg.classValue()) {
+ renamed_reg = map->lookup(flat_reg);
+ switch (flat_reg.classValue()) {
case InvalidRegClass:
break;
case IntRegClass:
@@ -1036,13 +1038,13 @@
break;
default:
- panic("Invalid register class: %d.", src_reg.classValue());
+ panic("Invalid register class: %d.", flat_reg.classValue());
}
DPRINTF(Rename,
"[tid:%i] "
"Looking up %s arch reg %i, got phys reg %i (%s)\n",
- tid, src_reg.className(),
+ tid, flat_reg.className(),
src_reg.index(), renamed_reg->index(),
renamed_reg->className());
@@ -1075,13 +1077,14 @@
gem5::ThreadContext *tc = inst->tcBase();
UnifiedRenameMap *map = renameMap[tid];
unsigned num_dest_regs = inst->numDestRegs();
+ auto *isa = tc->getIsaPtr();
// Rename the destination registers.
for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
const RegId& dest_reg = inst->destRegIdx(dest_idx);
UnifiedRenameMap::RenameInfo rename_result;
- RegId flat_dest_regid = tc->flattenRegId(dest_reg);
+ RegId flat_dest_regid = dest_reg.flatten(*isa);
flat_dest_regid.setNumPinnedWrites(dest_reg.getNumPinnedWrites());
rename_result = map->rename(flat_dest_regid);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 3ce225b..d996088 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -384,7 +384,7 @@
RegVal
getReg(const RegId &arch_reg) const override
{
- const RegId reg = flattenRegId(arch_reg);
+ const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
@@ -401,7 +401,7 @@
void
getReg(const RegId &arch_reg, void *val) const override
{
- const RegId reg = flattenRegId(arch_reg);
+ const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
@@ -417,7 +417,7 @@
void *
getWritableReg(const RegId &arch_reg) override
{
- const RegId reg = flattenRegId(arch_reg);
+ const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
auto ®_file = regFiles[reg.classValue()];
@@ -427,7 +427,7 @@
void
setReg(const RegId &arch_reg, RegVal val) override
{
- const RegId reg = flattenRegId(arch_reg);
+ const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
@@ -445,7 +445,7 @@
void
setReg(const RegId &arch_reg, const void *val) override
{
- const RegId reg = flattenRegId(arch_reg);
+ const RegId reg = arch_reg.flatten(*isa);
const RegIndex idx = reg.index();
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51233
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2a603c12bbc586720082363996f303cd3b43ac9c
Gerrit-Change-Number: 51233
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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