[gem5-dev] Change in gem5/gem5[develop]: cpu: Store the ISA class using BaseISA and not TheISA::ISA.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51238 )

Change subject: cpu: Store the ISA class using BaseISA and not TheISA::ISA.
......................................................................

cpu: Store the ISA class using BaseISA and not TheISA::ISA.

All generic functionality of the ISA class can now be accessed using
virtual methods, and so we don't need to keep the ISA specific version
of the class around any more.

Change-Id: I9f9a3de2dc68983276ef7efc008a18960412d509
---
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/fetch.cc
5 files changed, 18 insertions(+), 6 deletions(-)



diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 41c520a..314bcfd 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -216,7 +216,7 @@

     // Setup the rename map for whichever stages need it.
     for (ThreadID tid = 0; tid < numThreads; tid++) {
-        isa[tid] = dynamic_cast<TheISA::ISA *>(params.isa[tid]);
+        isa[tid] = params.isa[tid];
         commitRenameMap[tid].init(regClasses, &regFile, &freeList);
         renameMap[tid].init(regClasses, &regFile, &freeList);
     }
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e8c2150..b1f1bd2 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -451,7 +451,7 @@
     /** Integer Register Scoreboard */
     Scoreboard scoreboard;

-    std::vector<TheISA::ISA *> isa;
+    std::vector<BaseISA *> isa;

   public:
     /** Enum to give each stage a specific index, so when calling
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 5bbdc03..4aca76b 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -136,8 +136,7 @@
     branchPred = params.branchPred;

     for (ThreadID tid = 0; tid < numThreads; tid++) {
-        decoder[tid] = new TheISA::Decoder(
-                dynamic_cast<TheISA::ISA *>(params.isa[tid]));
+        decoder[tid] = new TheISA::Decoder(params.isa[tid]);
         // Create space to buffer the cache line data,
         // which may not hold the entire cache line.
         fetchBuffer[tid] = new uint8_t[fetchBufferSize];
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index cac5d6a..f3f8ebe 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -77,7 +77,7 @@
           {*_isa->regClasses().at(VecPredRegClass)},
           {*_isa->regClasses().at(CCRegClass)}
       }},
-      isa(dynamic_cast<TheISA::ISA *>(_isa)),
+      isa(_isa),
       predicate(true), memAccPredicate(true),
       comInstEventQueue("instruction-based event queue"),
       system(_sys), mmu(_mmu), decoder(isa),
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 22a8c7c..5a83e1e 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -161,7 +161,7 @@

     std::array<RegFile, CCRegClass + 1> regFiles;

-    TheISA::ISA *const isa;    // one "instance" of the current ISA.
+    BaseISA *const isa;    // one "instance" of the current ISA.

     TheISA::PCState _pcState;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9f9a3de2dc68983276ef7efc008a18960412d509
Gerrit-Change-Number: 51238
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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