Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51235 )
Change subject: arch: Remove unused register flattening methods.
......................................................................
arch: Remove unused register flattening methods.
Most flattening methods in the ISA classes aren't used. The one
exception is the flattenMiscIndex function in ARM.
Change-Id: I26088692fe3f56914009afb0203f59da7cf6023a
---
M src/arch/riscv/isa.hh
M src/arch/sparc/isa.hh
M src/arch/power/isa.hh
M src/arch/arm/isa.hh
M src/arch/x86/isa.hh
M src/arch/mips/isa.hh
6 files changed, 12 insertions(+), 226 deletions(-)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c8d7a7a..6468697 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -534,97 +534,6 @@
void setMiscRegNoEffect(int misc_reg, RegVal val);
void setMiscReg(int misc_reg, RegVal val);
- RegId
- flattenRegId(const RegId& regId) const
- {
- switch (regId.classValue()) {
- case IntRegClass:
- return intRegClass[flattenIntIndex(regId.index())];
- case FloatRegClass:
- panic("ARM doesn't use FloatRegClass.");
- case VecRegClass:
- return vecRegClass[flattenVecIndex(regId.index())];
- case VecElemClass:
- return vecElemClass[flattenVecElemIndex(regId.index())];
- case VecPredRegClass:
- return vecPredRegClass[flattenVecPredIndex(regId.index())];
- case CCRegClass:
- return ccRegClass[flattenCCIndex(regId.index())];
- case MiscRegClass:
- return miscRegClass[flattenMiscIndex(regId.index())];
- case InvalidRegClass:
- panic("Tried to flatten an invalid RegId.");
- }
- return RegId();
- }
-
- int
- flattenIntIndex(int reg) const
- {
- assert(reg >= 0);
- if (reg < int_reg::NumArchRegs) {
- return intRegMap[reg];
- } else if (reg < int_reg::NumRegs) {
- return reg;
- } else if (reg == int_reg::Spx) {
- CPSR cpsr = miscRegs[MISCREG_CPSR];
- ExceptionLevel el = opModeToEL(
- (OperatingMode) (uint8_t) cpsr.mode);
- if (!cpsr.sp && el != EL0)
- return int_reg::Sp0;
- switch (el) {
- case EL3:
- return int_reg::Sp3;
- case EL2:
- return int_reg::Sp2;
- case EL1:
- return int_reg::Sp1;
- case EL0:
- return int_reg::Sp0;
- default:
- panic("Invalid exception level");
- return 0; // Never happens.
- }
- } else {
- return flattenIntRegModeIndex(reg);
- }
- }
-
- int
- flattenFloatIndex(int reg) const
- {
- assert(reg >= 0);
- return reg;
- }
-
- int
- flattenVecIndex(int reg) const
- {
- assert(reg >= 0);
- return reg;
- }
-
- int
- flattenVecElemIndex(int reg) const
- {
- assert(reg >= 0);
- return reg;
- }
-
- int
- flattenVecPredIndex(int reg) const
- {
- assert(reg >= 0);
- return reg;
- }
-
- int
- flattenCCIndex(int reg) const
- {
- assert(reg >= 0);
- return reg;
- }
-
int
flattenMiscIndex(int reg) const
{
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index e8acb14..2b041e3 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -135,17 +135,6 @@
public:
ISA(const Params &p);
- RegId flattenRegId(const RegId& regId) const { return regId; }
-
- int flattenIntIndex(int reg) const { return reg; }
- int flattenFloatIndex(int reg) const { return reg; }
- int flattenVecIndex(int reg) const { return reg; }
- int flattenVecElemIndex(int reg) const { return reg; }
- int flattenVecPredIndex(int reg) const { return reg; }
- // dummy
- int flattenCCIndex(int reg) const { return reg; }
- int flattenMiscIndex(int reg) const { return reg; }
-
bool
inUserMode() const override
{
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index d563ebe..0ac96b0 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -85,51 +85,6 @@
fatal("Power does not currently have any misc regs defined\n");
}
- RegId flattenRegId(const RegId& regId) const { return regId; }
-
- int
- flattenIntIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenFloatIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecElemIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecPredIndex(int reg) const
- {
- return reg;
- }
-
- // dummy
- int
- flattenCCIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenMiscIndex(int reg) const
- {
- return reg;
- }
-
bool
inUserMode() const override
{
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 4521c52..2270846 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -82,15 +82,6 @@
void setMiscRegNoEffect(int misc_reg, RegVal val);
void setMiscReg(int misc_reg, RegVal val);
- RegId flattenRegId(const RegId ®Id) const { return regId; }
- int flattenIntIndex(int reg) const { return reg; }
- int flattenFloatIndex(int reg) const { return reg; }
- int flattenVecIndex(int reg) const { return reg; }
- int flattenVecElemIndex(int reg) const { return reg; }
- int flattenVecPredIndex(int reg) const { return reg; }
- int flattenCCIndex(int reg) const { return reg; }
- int flattenMiscIndex(int reg) const { return reg; }
-
bool inUserMode() const override { return true; }
void copyRegsFrom(ThreadContext *src) override;
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 6be7ba7..ae6980f 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -187,40 +187,6 @@
void setMiscRegNoEffect(int miscReg, RegVal val);
void setMiscReg(int miscReg, RegVal val);
- RegId
- flattenRegId(const RegId& regId) const
- {
- switch (regId.classValue()) {
- case IntRegClass:
- return intRegClass[flattenIntIndex(regId.index())];
- case FloatRegClass:
- return floatRegClass[flattenFloatIndex(regId.index())];
- case MiscRegClass:
- return miscRegClass[flattenMiscIndex(regId.index())];
- default:
- break;
- }
- return regId;
- }
-
- int
- flattenIntIndex(int reg) const
- {
- assert(reg < TotalInstIntRegs);
- RegIndex flatIndex = intRegMap[reg];
- assert(flatIndex < int_reg::NumRegs);
- return flatIndex;
- }
-
- int flattenFloatIndex(int reg) const { return reg; }
- int flattenVecIndex(int reg) const { return reg; }
- int flattenVecElemIndex(int reg) const { return reg; }
- int flattenVecPredIndex(int reg) const { return reg; }
-
- // dummy
- int flattenCCIndex(int reg) const { return reg; }
- int flattenMiscIndex(int reg) const { return reg; }
-
uint64_t
getExecutingAsid() const override
{
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index fdfc1c2..9e78e00 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -71,42 +71,6 @@
void setMiscRegNoEffect(int miscReg, RegVal val);
void setMiscReg(int miscReg, RegVal val);
- RegId
- flattenRegId(const RegId& regId) const
- {
- switch (regId.classValue()) {
- case IntRegClass:
- return intRegClass[flattenIntIndex(regId.index())];
- case FloatRegClass:
- return floatRegClass[flattenFloatIndex(regId.index())];
- case CCRegClass:
- return ccRegClass[flattenCCIndex(regId.index())];
- case MiscRegClass:
- return miscRegClass[flattenMiscIndex(regId.index())];
- default:
- break;
- }
- return regId;
- }
-
- int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; }
-
- int
- flattenFloatIndex(int reg) const
- {
- if (reg >= float_reg::NumRegs) {
- reg = float_reg::stack(reg - float_reg::NumRegs,
- regVal[misc_reg::X87Top]);
- }
- return reg;
- }
-
- int flattenVecIndex(int reg) const { return reg; }
- int flattenVecElemIndex(int reg) const { return reg; }
- int flattenVecPredIndex(int reg) const { return reg; }
- int flattenCCIndex(int reg) const { return reg; }
- int flattenMiscIndex(int reg) const { return reg; }
-
bool
inUserMode() const override
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I26088692fe3f56914009afb0203f59da7cf6023a
Gerrit-Change-Number: 51235
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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