[gem5-dev] Change in gem5/gem5[develop]: fastmodel,cpu: Remove the flattenRegId ThreadContext method.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51234 )

Change subject: fastmodel,cpu: Remove the flattenRegId ThreadContext method.
......................................................................

fastmodel,cpu: Remove the flattenRegId ThreadContext method.

This is no longer used or necessary.

Change-Id: Ide8dd74b5d39b245d3d71979dd84c7fee60d566e
---
M src/cpu/simple_thread.hh
M src/cpu/o3/thread_context.cc
M src/cpu/o3/thread_context.hh
M src/cpu/thread_context.hh
M src/cpu/checker/thread_context.hh
M src/arch/arm/fastmodel/iris/thread_context.hh
6 files changed, 11 insertions(+), 28 deletions(-)



diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh
index 05e06e3..51fc34e 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -362,12 +362,6 @@
         setMiscRegNoEffect(misc_reg, val);
     }

-    RegId
-    flattenRegId(const RegId& regId) const override
-    {
-        panic("%s not implemented.", __FUNCTION__);
-    }
-
     // Also not necessarily the best location for these two.  Hopefully  
will go
     // away once we decide upon where st cond failures goes.
     unsigned
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh
index 3cb97a3..27a0323 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -324,12 +324,6 @@
         actualTC->setMiscReg(misc_reg, val);
     }

-    RegId
-    flattenRegId(const RegId& regId) const override
-    {
-        return actualTC->flattenRegId(regId);
-    }
-
     unsigned
     readStCondFailures() const override
     {
diff --git a/src/cpu/o3/thread_context.cc b/src/cpu/o3/thread_context.cc
index 836dd53..8a4d9a8 100644
--- a/src/cpu/o3/thread_context.cc
+++ b/src/cpu/o3/thread_context.cc
@@ -196,12 +196,6 @@
     conditionalSquash();
 }

-RegId
-ThreadContext::flattenRegId(const RegId& regId) const
-{
-    return cpu->isa[thread->threadId()]->flattenRegId(regId);
-}
-
 void
 ThreadContext::setMiscRegNoEffect(RegIndex misc_reg, RegVal val)
 {
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 2876f7f..e2777b6 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -231,8 +231,6 @@
      * write might have as defined by the architecture. */
     void setMiscReg(RegIndex misc_reg, RegVal val) override;

-    RegId flattenRegId(const RegId& regId) const override;
-
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
     unsigned
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index d996088..22a8c7c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -355,12 +355,6 @@
         return isa->setMiscReg(misc_reg, val);
     }

-    RegId
-    flattenRegId(const RegId& regId) const override
-    {
-        return isa->flattenRegId(regId);
-    }
-
     unsigned readStCondFailures() const override { return  
storeCondFailures; }

     bool
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 6d4397a..8972c7e 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -226,8 +226,6 @@

     virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;

-    virtual RegId flattenRegId(const RegId& reg_id) const = 0;
-
     // Also not necessarily the best location for these two.  Hopefully  
will go
     // away once we decide upon where st cond failures goes.
     virtual unsigned readStCondFailures() const = 0;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ide8dd74b5d39b245d3d71979dd84c7fee60d566e
Gerrit-Change-Number: 51234
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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