[gem5-dev] Change in gem5/gem5[develop]: arch: Make the ISA::clear() method virtual.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/51236 )

Change subject: arch: Make the ISA::clear() method virtual.
......................................................................

arch: Make the ISA::clear() method virtual.

This method is not at all on the critical path, and the adding virtual
method overhead to it will have essentially no effect on over all
performance.

Change-Id: I583bbe30f5ed923a0c771f36c3f07e5979c28476
---
M src/arch/generic/isa.hh
M src/arch/riscv/isa.hh
M src/arch/sparc/isa.hh
M src/arch/power/isa.hh
M src/arch/arm/isa.hh
M src/arch/x86/isa.hh
M src/arch/mips/isa.hh
7 files changed, 20 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 6468697..8c30e8b 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -502,7 +502,7 @@
         void assert64() {  
assert(!((CPSR)readMiscReg(MISCREG_CPSR)).width); }

       public:
-        void clear();
+        void clear() override;

       protected:
         void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 8658e22..95bfb5b 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -66,6 +66,8 @@
     RegClasses _regClasses;

   public:
+    virtual void clear() {}
+
     virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext  
*old_tc) {}
     virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 2b041e3..4f937e3 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -76,7 +76,7 @@
         std::vector<BankType> bankType;

       public:
-        void clear();
+        void clear() override;

       public:
         void configCP();
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 0ac96b0..8fe50b5 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -56,9 +56,6 @@
     RegVal miscRegs[NUM_MISCREGS];

   public:
-    void clear() {}
-
-  public:
     RegVal
     readMiscRegNoEffect(int misc_reg) const
     {
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 2270846..d68596e 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -74,7 +74,7 @@
   public:
     using Params = RiscvISAParams;

-    void clear();
+    void clear() override;

   public:
     RegVal readMiscRegNoEffect(int misc_reg) const;
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index ae6980f..be78975 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -169,7 +169,7 @@
   public:
     const RegIndex &mapIntRegId(RegIndex idx) const { return  
intRegMap[idx]; }

-    void clear();
+    void clear() override;

     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 9e78e00..17dfb4c 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -59,7 +59,7 @@
     std::string vendorString;

   public:
-    void clear();
+    void clear() override;

     using Params = X86ISAParams;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I583bbe30f5ed923a0c771f36c3f07e5979c28476
Gerrit-Change-Number: 51236
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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