Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51672 )
Change subject: arch-arm, dev-arm: Use PageTableOps in Arm TableWalker
......................................................................
arch-arm, dev-arm: Use PageTableOps in Arm TableWalker
As the VMSA is shared between the CPU MMU and the SMMU, we move the
PageTableOps data structures to the arch/arm/pagetable.hh/cc sources.
Both MMUs will make use of them
Change-Id: I3a1113f6ef56f8d879aff2df50a01037baca82ff
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3.hh
R src/arch/arm/pagetable.cc
M src/arch/arm/pagetable.hh
D src/dev/arm/smmu_v3_ptops.hh
M src/dev/arm/smmu_v3_transl.cc
M src/dev/arm/smmu_v3_transl.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/dev/arm/SConscript
M src/arch/arm/SConscript
11 files changed, 219 insertions(+), 239 deletions(-)
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index ac004dd..56c4f86 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -82,6 +82,7 @@
Source('regs/misc.cc')
Source('mmu.cc')
Source('nativetrace.cc')
+ Source('pagetable.cc')
Source('pauth_helpers.cc')
Source('pmu.cc')
Source('process.cc')
diff --git a/src/dev/arm/smmu_v3_ptops.cc b/src/arch/arm/pagetable.cc
similarity index 83%
rename from src/dev/arm/smmu_v3_ptops.cc
rename to src/arch/arm/pagetable.cc
index 058cca4..4987aa7 100644
--- a/src/dev/arm/smmu_v3_ptops.cc
+++ b/src/arch/arm/pagetable.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, 2018-2019 ARM Limited
+ * Copyright (c) 2013, 2018-2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -35,7 +35,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "dev/arm/smmu_v3_ptops.hh"
+#include "arch/arm/pagetable.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
@@ -43,6 +43,14 @@
namespace gem5
{
+namespace ArmISA
+{
+
+const GrainSize GrainMap_tg0[] =
+ { Grain4KB, Grain64KB, Grain16KB, ReservedGrain };
+const GrainSize GrainMap_tg1[] =
+ { ReservedGrain, Grain16KB, Grain4KB, Grain64KB };
+
bool
V7LPageTableOps::isValid(pte_t pte, unsigned level) const
{
@@ -122,16 +130,16 @@
}
}
-unsigned
+LookupLevel
V7LPageTableOps::firstLevel(uint8_t tsz) const
{
- return 1;
+ return L1;
}
-unsigned
+LookupLevel
V7LPageTableOps::lastLevel() const
{
- return 3;
+ return L3;
}
bool
@@ -216,20 +224,31 @@
}
}
-unsigned
+LookupLevel
V8PageTableOps4k::firstLevel(uint8_t tsz) const
{
- if (tsz >= 16 && tsz <= 24) return 0;
- if (tsz >= 25 && tsz <= 33) return 1;
- if (tsz >= 34 && tsz <= 39) return 2;
+ if (tsz >= 16 && tsz <= 24) return L0;
+ if (tsz >= 25 && tsz <= 33) return L1;
+ if (tsz >= 34 && tsz <= 39) return L2;
panic("Unsupported TnSZ: %d\n", tsz);
}
-unsigned
+LookupLevel
+V8PageTableOps4k::firstS2Level(uint8_t sl0) const
+{
+ switch (sl0) {
+ case 0: return L2;
+ case 1: return L1;
+ case 2: return L0;
+ default: panic("Unsupported VTCR_EL2.SL0: %d", sl0);
+ }
+}
+
+LookupLevel
V8PageTableOps4k::lastLevel() const
{
- return 3;
+ return L3;
}
bool
@@ -316,21 +335,32 @@
}
}
-unsigned
+LookupLevel
V8PageTableOps16k::firstLevel(uint8_t tsz) const
{
- if (tsz == 16) return 0;
- if (tsz >= 17 && tsz <= 27) return 1;
- if (tsz >= 28 && tsz <= 38) return 2;
- if (tsz == 39) return 3;
+ if (tsz == 16) return L0;
+ if (tsz >= 17 && tsz <= 27) return L1;
+ if (tsz >= 28 && tsz <= 38) return L2;
+ if (tsz == 39) return L3;
panic("Unsupported TnSZ: %d\n", tsz);
}
-unsigned
+LookupLevel
+V8PageTableOps16k::firstS2Level(uint8_t sl0) const
+{
+ switch (sl0) {
+ case 0: return L3;
+ case 1: return L2;
+ case 2: return L1;
+ default: panic("Unsupported VTCR_EL2.SL0: %d", sl0);
+ }
+}
+
+LookupLevel
V8PageTableOps16k::lastLevel() const
{
- return 3;
+ return L3;
}
bool
@@ -409,20 +439,48 @@
}
}
-unsigned
+LookupLevel
V8PageTableOps64k::firstLevel(uint8_t tsz) const
{
- if (tsz >= 12 && tsz <= 21) return 1;
- if (tsz >= 22 && tsz <= 34) return 2;
- if (tsz >= 35 && tsz <= 39) return 3;
+ if (tsz >= 12 && tsz <= 21) return L1;
+ if (tsz >= 22 && tsz <= 34) return L2;
+ if (tsz >= 35 && tsz <= 39) return L3;
panic("Unsupported TnSZ: %d\n", tsz);
}
-unsigned
-V8PageTableOps64k::lastLevel() const
+LookupLevel
+V8PageTableOps64k::firstS2Level(uint8_t sl0) const
{
- return 3;
+ switch (sl0) {
+ case 0: return L3;
+ case 1: return L2;
+ case 2: return L1;
+ default: panic("Unsupported VTCR_EL2.SL0: %d", sl0);
+ }
}
+LookupLevel
+V8PageTableOps64k::lastLevel() const
+{
+ return L3;
+}
+
+const PageTableOps *
+getPageTableOps(GrainSize trans_granule)
+{
+ static V8PageTableOps4k ptOps4k;
+ static V8PageTableOps16k ptOps16k;
+ static V8PageTableOps64k ptOps64k;
+
+ switch (trans_granule) {
+ case Grain4KB: return &ptOps4k;
+ case Grain16KB: return &ptOps16k;
+ case Grain64KB: return &ptOps64k;
+ default:
+ panic("Unknown translation granule size %d", trans_granule);
+ }
+}
+
+} // namespace ArmISA
} // namespace gem5
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 9145890..b03320a 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -56,6 +56,28 @@
namespace ArmISA
{
+// Lookup level
+enum LookupLevel
+{
+ L0 = 0, // AArch64 only
+ L1,
+ L2,
+ L3,
+ MAX_LOOKUP_LEVELS
+};
+
+// Granule sizes
+enum GrainSize
+{
+ Grain4KB = 12,
+ Grain16KB = 14,
+ Grain64KB = 16,
+ ReservedGrain = 0
+};
+
+extern const GrainSize GrainMap_tg0[];
+extern const GrainSize GrainMap_tg1[];
+
// Max. physical address range in bits supported by the architecture
const unsigned MaxPhysAddrRange = 52;
@@ -74,14 +96,75 @@
};
-// Lookup level
-enum LookupLevel
+struct PageTableOps
{
- L0 = 0, // AArch64 only
- L1,
- L2,
- L3,
- MAX_LOOKUP_LEVELS
+ typedef int64_t pte_t;
+
+ virtual bool isValid(pte_t pte, unsigned level) const = 0;
+ virtual bool isLeaf(pte_t pte, unsigned level) const = 0;
+ virtual bool isWritable(pte_t pte, unsigned level, bool stage2) const
= 0;
+ virtual Addr nextLevelPointer(pte_t pte, unsigned level) const = 0;
+ virtual Addr index(Addr va, unsigned level) const = 0;
+ virtual Addr pageMask(pte_t pte, unsigned level) const = 0;
+ virtual Addr walkMask(unsigned level) const = 0;
+ virtual LookupLevel firstLevel(uint8_t tsz) const = 0;
+ virtual LookupLevel firstS2Level(uint8_t sl0) const = 0;
+ virtual LookupLevel lastLevel() const = 0;
+};
+
+struct V7LPageTableOps : public PageTableOps
+{
+ bool isValid(pte_t pte, unsigned level) const override;
+ bool isLeaf(pte_t pte, unsigned level) const override;
+ bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
+ Addr nextLevelPointer(pte_t pte, unsigned level) const override;
+ Addr index(Addr va, unsigned level) const override;
+ Addr pageMask(pte_t pte, unsigned level) const override;
+ Addr walkMask(unsigned level) const override;
+ LookupLevel firstLevel(uint8_t tsz) const override;
+ LookupLevel lastLevel() const override;
+};
+
+struct V8PageTableOps4k : public PageTableOps
+{
+ bool isValid(pte_t pte, unsigned level) const override;
+ bool isLeaf(pte_t pte, unsigned level) const override;
+ bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
+ Addr nextLevelPointer(pte_t pte, unsigned level) const override;
+ Addr index(Addr va, unsigned level) const override;
+ Addr pageMask(pte_t pte, unsigned level) const override;
+ Addr walkMask(unsigned level) const override;
+ LookupLevel firstLevel(uint8_t tsz) const override;
+ LookupLevel firstS2Level(uint8_t sl0) const override;
+ LookupLevel lastLevel() const override;
+};
+
+struct V8PageTableOps16k : public PageTableOps
+{
+ bool isValid(pte_t pte, unsigned level) const override;
+ bool isLeaf(pte_t pte, unsigned level) const override;
+ bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
+ Addr nextLevelPointer(pte_t pte, unsigned level) const override;
+ Addr index(Addr va, unsigned level) const override;
+ Addr pageMask(pte_t pte, unsigned level) const override;
+ Addr walkMask(unsigned level) const override;
+ LookupLevel firstLevel(uint8_t tsz) const override;
+ LookupLevel firstS2Level(uint8_t sl0) const override;
+ LookupLevel lastLevel() const override;
+};
+
+struct V8PageTableOps64k : public PageTableOps
+{
+ bool isValid(pte_t pte, unsigned level) const override;
+ bool isLeaf(pte_t pte, unsigned level) const override;
+ bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
+ Addr nextLevelPointer(pte_t pte, unsigned level) const override;
+ Addr index(Addr va, unsigned level) const override;
+ Addr pageMask(pte_t pte, unsigned level) const override;
+ Addr walkMask(unsigned level) const override;
+ LookupLevel firstLevel(uint8_t tsz) const override;
+ LookupLevel firstS2Level(uint8_t sl0) const override;
+ LookupLevel lastLevel() const override;
};
// ITB/DTB table entry
@@ -389,6 +472,8 @@
};
+const PageTableOps *getPageTableOps(GrainSize trans_granule);
+
} // namespace ArmISA
} // namespace gem5
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 73bcc5c..167b5d2 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -41,6 +41,7 @@
#include "arch/arm/faults.hh"
#include "arch/arm/mmu.hh"
+#include "arch/arm/pagetable.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "base/compiler.hh"
@@ -873,11 +874,6 @@
DPRINTF(TLB, "Beginning table walk for address %#llx, TCR: %#llx\n",
currState->vaddr_tainted, currState->tcr);
- static const GrainSize GrainMap_tg0[] =
- { Grain4KB, Grain64KB, Grain16KB, ReservedGrain };
- static const GrainSize GrainMap_tg1[] =
- { ReservedGrain, Grain16KB, Grain4KB, Grain64KB };
-
stats.walkWaitTime.sample(curTick() - currState->startTime);
// Determine TTBR, table size, granule size and phys. address range
@@ -953,18 +949,10 @@
}
tsz = 64 - currState->vtcr.t0sz64;
tg = GrainMap_tg0[currState->vtcr.tg0];
- // ARM DDI 0487A.f D7-2148
- // The starting level of stage 2 translation depends on
- // VTCR_EL2.SL0 and VTCR_EL2.TG0
- LookupLevel __ = MAX_LOOKUP_LEVELS; // invalid level
- uint8_t sl_tg = (currState->vtcr.sl0 << 2) |
currState->vtcr.tg0;
- static const LookupLevel SLL[] = {
- L2, L3, L3, __, // sl0 == 0
- L1, L2, L2, __, // sl0 == 1, etc.
- L0, L1, L1, __,
- __, __, __, __
- };
- start_lookup_level = SLL[sl_tg];
+
+ start_lookup_level = getPageTableOps(tg)->firstS2Level(
+ currState->vtcr.sl0);
+
panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
"Cannot discern lookup level from vtcr.{sl0,tg0}");
ps = currState->vtcr.ps;
@@ -1100,39 +1088,10 @@
}
// Determine starting lookup level
- // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library
- // in ARM DDI 0487A. These table values correspond to the cascading
tests
- // to compute the lookup level and are of the form
- // (grain_size + N*stride), for N = {1, 2, 3}.
- // A value of 64 will never succeed and a value of 0 will always
succeed.
if (start_lookup_level == MAX_LOOKUP_LEVELS) {
- struct GrainMap
- {
- GrainSize grain_size;
- unsigned lookup_level_cutoff[MAX_LOOKUP_LEVELS];
- };
- static const GrainMap GM[] = {
- { Grain4KB, { 39, 30, 0, 0 } },
- { Grain16KB, { 47, 36, 25, 0 } },
- { Grain64KB, { 64, 42, 29, 0 } }
- };
+ const auto* ptops = getPageTableOps(tg);
- const unsigned *lookup = NULL; // points to a lookup_level_cutoff
-
- for (unsigned i = 0; i < 3; ++i) { // choose entry of GM[]
- if (tg == GM[i].grain_size) {
- lookup = GM[i].lookup_level_cutoff;
- break;
- }
- }
- assert(lookup);
-
- for (int L = L0; L != MAX_LOOKUP_LEVELS; ++L) {
- if (tsz > lookup[L]) {
- start_lookup_level = (LookupLevel) L;
- break;
- }
- }
+ start_lookup_level = ptops->firstLevel(64 - tsz);
panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
"Table walker couldn't find lookup level\n");
}
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 77fb7fc..027806e 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -372,15 +372,6 @@
};
- // Granule sizes for AArch64 long descriptors
- enum GrainSize
- {
- Grain4KB = 12,
- Grain16KB = 14,
- Grain64KB = 16,
- ReservedGrain = 0
- };
-
/** Long-descriptor format (LPAE) */
class LongDescriptor : public DescriptorBase
{
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index a33b37d..ba7348c 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -77,7 +77,6 @@
Source('smmu_v3_events.cc');
Source('smmu_v3_ports.cc');
Source('smmu_v3_proc.cc');
- Source('smmu_v3_ptops.cc');
Source('smmu_v3_deviceifc.cc');
Source('smmu_v3_transl.cc');
Source('timer_sp804.cc')
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index 03fe2ef..41f7424e 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -567,22 +567,6 @@
}
}
-const PageTableOps*
-SMMUv3::getPageTableOps(uint8_t trans_granule)
-{
- static V8PageTableOps4k ptOps4k;
- static V8PageTableOps16k ptOps16k;
- static V8PageTableOps64k ptOps64k;
-
- switch (trans_granule) {
- case TRANS_GRANULE_4K: return &ptOps4k;
- case TRANS_GRANULE_16K: return &ptOps16k;
- case TRANS_GRANULE_64K: return &ptOps64k;
- default:
- panic("Unknown translation granule size %d", trans_granule);
- }
-}
-
Tick
SMMUv3::readControl(PacketPtr pkt)
{
diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh
index 8169da7..25b91ff 100644
--- a/src/dev/arm/smmu_v3.hh
+++ b/src/dev/arm/smmu_v3.hh
@@ -52,7 +52,6 @@
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
-#include "dev/arm/smmu_v3_ptops.hh"
#include "mem/packet.hh"
#include "params/SMMUv3.hh"
#include "sim/clocked_object.hh"
@@ -172,8 +171,6 @@
void processCommand(const SMMUCommand &cmd);
- const PageTableOps *getPageTableOps(uint8_t trans_granule);
-
public:
SMMUv3(const SMMUv3Params &p);
virtual ~SMMUv3() {}
diff --git a/src/dev/arm/smmu_v3_ptops.hh b/src/dev/arm/smmu_v3_ptops.hh
deleted file mode 100644
index 2e025f8..0000000
--- a/src/dev/arm/smmu_v3_ptops.hh
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (c) 2013, 2018-2019 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __DEV_ARM_SMMU_V3_PTOPS_HH__
-#define __DEV_ARM_SMMU_V3_PTOPS_HH__
-
-#include <stdint.h>
-
-#include "base/types.hh"
-
-namespace gem5
-{
-
-struct PageTableOps
-{
- typedef int64_t pte_t;
-
- virtual bool isValid(pte_t pte, unsigned level) const = 0;
- virtual bool isLeaf(pte_t pte, unsigned level) const = 0;
- virtual bool isWritable(pte_t pte, unsigned level, bool stage2) const
= 0;
- virtual Addr nextLevelPointer(pte_t pte, unsigned level) const = 0;
- virtual Addr index(Addr va, unsigned level) const = 0;
- virtual Addr pageMask(pte_t pte, unsigned level) const = 0;
- virtual Addr walkMask(unsigned level) const = 0;
- virtual unsigned firstLevel(uint8_t tsz) const = 0;
- virtual unsigned lastLevel() const = 0;
-};
-
-struct V7LPageTableOps : public PageTableOps
-{
- bool isValid(pte_t pte, unsigned level) const override;
- bool isLeaf(pte_t pte, unsigned level) const override;
- bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
- Addr nextLevelPointer(pte_t pte, unsigned level) const override;
- Addr index(Addr va, unsigned level) const override;
- Addr pageMask(pte_t pte, unsigned level) const override;
- Addr walkMask(unsigned level) const override;
- unsigned firstLevel(uint8_t tsz) const override;
- unsigned lastLevel() const override;
-};
-
-struct V8PageTableOps4k : public PageTableOps
-{
- bool isValid(pte_t pte, unsigned level) const override;
- bool isLeaf(pte_t pte, unsigned level) const override;
- bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
- Addr nextLevelPointer(pte_t pte, unsigned level) const override;
- Addr index(Addr va, unsigned level) const override;
- Addr pageMask(pte_t pte, unsigned level) const override;
- Addr walkMask(unsigned level) const override;
- unsigned firstLevel(uint8_t tsz) const override;
- unsigned lastLevel() const override;
-};
-
-struct V8PageTableOps16k : public PageTableOps
-{
- bool isValid(pte_t pte, unsigned level) const override;
- bool isLeaf(pte_t pte, unsigned level) const override;
- bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
- Addr nextLevelPointer(pte_t pte, unsigned level) const override;
- Addr index(Addr va, unsigned level) const override;
- Addr pageMask(pte_t pte, unsigned level) const override;
- Addr walkMask(unsigned level) const override;
- unsigned firstLevel(uint8_t tsz) const override;
- unsigned lastLevel() const override;
-};
-
-struct V8PageTableOps64k : public PageTableOps
-{
- bool isValid(pte_t pte, unsigned level) const override;
- bool isLeaf(pte_t pte, unsigned level) const override;
- bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
- Addr nextLevelPointer(pte_t pte, unsigned level) const override;
- Addr index(Addr va, unsigned level) const override;
- Addr pageMask(pte_t pte, unsigned level) const override;
- Addr walkMask(unsigned level) const override;
- unsigned firstLevel(uint8_t tsz) const override;
- unsigned lastLevel() const override;
-};
-
-} // namespace gem5
-
-#endif /* __DEV_ARM_SMMU_V3_PTOPS_HH__ */
diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index 4c88ee1..e94d2af 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, 2018-2019 ARM Limited
+ * Copyright (c) 2013, 2018-2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -37,6 +37,7 @@
#include "dev/arm/smmu_v3_transl.hh"
+#include "arch/arm/pagetable.hh"
#include "debug/SMMUv3.hh"
#include "debug/SMMUv3Hazard.hh"
#include "dev/arm/amba.hh"
@@ -46,6 +47,8 @@
namespace gem5
{
+using namespace ArmISA;
+
SMMUTranslRequest
SMMUTranslRequest::fromPacket(PacketPtr pkt, bool ats)
{
@@ -657,10 +660,11 @@
const char *indent = stage==2 ? " " : "";
(void) indent; // this is only used in DPRINTFs
- const PageTableOps *pt_ops =
- stage == 1 ?
- smmu.getPageTableOps(context.stage1TranslGranule) :
- smmu.getPageTableOps(context.stage2TranslGranule);
+ const auto tg = stage == 1 ?
+ GrainMap_tg0[context.stage1TranslGranule] :
+ GrainMap_tg0[context.stage2TranslGranule];
+
+ const auto *pt_ops = getPageTableOps(tg);
unsigned walkCacheLevels =
smmu.walkCacheEnable ?
@@ -882,8 +886,8 @@
SMMUTranslationProcess::TranslResult
SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
{
- const PageTableOps *pt_ops =
- smmu.getPageTableOps(context.stage1TranslGranule);
+ const auto tg = GrainMap_tg0[context.stage1TranslGranule];
+ const auto *pt_ops = getPageTableOps(tg);
const WalkCache::Entry *walk_ep = NULL;
unsigned level;
@@ -938,8 +942,8 @@
SMMUTranslationProcess::TranslResult
SMMUTranslationProcess::translateStage2(Yield &yield, Addr addr, bool
final_tr)
{
- const PageTableOps *pt_ops =
- smmu.getPageTableOps(context.stage2TranslGranule);
+ const auto tg = GrainMap_tg0[context.stage2TranslGranule];
+ const auto *pt_ops = getPageTableOps(tg);
const IPACache::Entry *ipa_ep = NULL;
if (smmu.ipaCacheEnable) {
diff --git a/src/dev/arm/smmu_v3_transl.hh b/src/dev/arm/smmu_v3_transl.hh
index 0cd4908..156d3e6 100644
--- a/src/dev/arm/smmu_v3_transl.hh
+++ b/src/dev/arm/smmu_v3_transl.hh
@@ -41,12 +41,16 @@
#include "base/compiler.hh"
#include "dev/arm/smmu_v3_deviceifc.hh"
#include "dev/arm/smmu_v3_proc.hh"
-#include "dev/arm/smmu_v3_ptops.hh"
#include "mem/packet.hh"
namespace gem5
{
+namespace ArmISA
+{
+struct PageTableOps;
+}
+
struct SMMUTranslRequest
{
Addr addr;
@@ -129,11 +133,11 @@
bool leaf, uint8_t permissions);
TranslResult walkStage1And2(Yield &yield, Addr addr,
- const PageTableOps *pt_ops,
+ const ArmISA::PageTableOps *pt_ops,
unsigned level, Addr walkPtr);
TranslResult walkStage2(Yield &yield, Addr addr, bool final_tr,
- const PageTableOps *pt_ops,
+ const ArmISA::PageTableOps *pt_ops,
unsigned level, Addr walkPtr);
TranslResult translateStage1And2(Yield &yield, Addr addr);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3a1113f6ef56f8d879aff2df50a01037baca82ff
Gerrit-Change-Number: 51672
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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