Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51671 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: EL2&0 invalidations do not depend on VMID
......................................................................
arch-arm: EL2&0 invalidations do not depend on VMID
When the PE is executing in host mode (HCR.E2H = HCR.TGE = 1)
The invalidation shouldn't depend on the current VMID
Change-Id: I3433485cc8f8dedb657139bcc3d71e05e9d7e4f1
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51671
Tested-by: kokoro <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlb.cc
2 files changed, 34 insertions(+), 4 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5f3e2d7..e2897f8 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -350,8 +350,14 @@
te = &table[x];
const bool el_match = te->checkELMatch(
tlbi_op.targetEL, tlbi_op.inHost);
+
+ const bool vmid_match =
+ te->vmid == vmid ||
+ !tlbi_op.el2Enabled ||
+ (!tlbi_op.stage2Flush() && tlbi_op.inHost);
+
if (te->valid && tlbi_op.secureLookup == !te->nstid &&
- (te->vmid == vmid || !tlbi_op.el2Enabled) && el_match) {
+ el_match && vmid_match) {
DPRINTF(TLB, " - %s\n", te->print());
te->valid = false;
@@ -432,10 +438,16 @@
while (x < size) {
te = &table[x];
+
+ const bool el_match = te->checkELMatch(
+ tlbi_op.targetEL, tlbi_op.inHost);
+
+ const bool vmid_match =
+ te->vmid == vmid || !tlbi_op.el2Enabled || tlbi_op.inHost;
+
if (te->valid && te->asid == tlbi_op.asid &&
tlbi_op.secureLookup == !te->nstid &&
- (te->vmid == vmid || tlbi_op.el2Enabled) &&
- te->checkELMatch(tlbi_op.targetEL, tlbi_op.inHost)) {
+ vmid_match && el_match) {
te->valid = false;
DPRINTF(TLB, " - %s\n", te->print());
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index 5f2cc5a..5c595a8 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020 ARM Limited
+ * Copyright (c) 2018-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -95,6 +95,7 @@
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
+ el2Enabled = EL2Enabled(tc);
getMMUPtr(tc)->flush(*this);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3433485cc8f8dedb657139bcc3d71e05e9d7e4f1
Gerrit-Change-Number: 51671
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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