Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51449 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: python,configs: Add Ruby support to RISC-V board
......................................................................
python,configs: Add Ruby support to RISC-V board
Take out guards stopping the RISC-V board from being configured with
Ruby and update the I/O config with a check for Ruby. Also, add a
comment in the example file that Ruby is now supported.
Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Signed-off-by: Jason Lowe-Power <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51449
Tested-by: kokoro <[email protected]>
Reviewed-by: Bobby R. Bruce <[email protected]>
Maintainer: Bobby R. Bruce <[email protected]>
---
M src/python/gem5/components/boards/riscv_board.py
M configs/example/components-library/riscv_fs.py
2 files changed, 40 insertions(+), 17 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/components-library/riscv_fs.py
b/configs/example/components-library/riscv_fs.py
index eadac8b..9b9d5f0 100644
--- a/configs/example/components-library/riscv_fs.py
+++ b/configs/example/components-library/riscv_fs.py
@@ -57,7 +57,9 @@
PrivateL1PrivateL2CacheHierarchy,
)
-# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been
tested.
+# Setup the cache hierarchy.
+# For classic, PrivateL1PrivateL2 and NoCache have been tested.
+# For Ruby, MESI_Two_Level and MI_example have been tested.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
)
diff --git a/src/python/gem5/components/boards/riscv_board.py
b/src/python/gem5/components/boards/riscv_board.py
index a41f33f..d42cfd5 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -89,9 +89,6 @@
requires(isa_required=ISA.RISCV)
- if cache_hierarchy.is_ruby():
- raise EnvironmentError("RiscvBoard is not compatible with
Ruby")
-
self.workload = RiscvLinux()
# Contains a CLINT, PLIC, UART, and some functions for the dtb,
etc.
@@ -124,20 +121,26 @@
def _setup_io_devices(self) -> None:
"""Connect the I/O devices to the I/O bus"""
- for device in self._off_chip_devices:
- device.pio = self.iobus.mem_side_ports
- for device in self._on_chip_devices:
- device.pio = self.get_cache_hierarchy().get_mem_side_port()
- self.bridge = Bridge(delay="10ns")
- self.bridge.mem_side_port = self.iobus.cpu_side_ports
- self.bridge.cpu_side_port = (
- self.get_cache_hierarchy().get_mem_side_port()
- )
- self.bridge.ranges = [
- AddrRange(dev.pio_addr, size=dev.pio_size)
- for dev in self._off_chip_devices
- ]
+ if self.get_cache_hierarchy().is_ruby():
+ for device in self._off_chip_devices + self._on_chip_devices:
+ device.pio = self.iobus.mem_side_ports
+
+ else:
+ for device in self._off_chip_devices:
+ device.pio = self.iobus.mem_side_ports
+ for device in self._on_chip_devices:
+ device.pio = self.get_cache_hierarchy().get_mem_side_port()
+
+ self.bridge = Bridge(delay="10ns")
+ self.bridge.mem_side_port = self.iobus.cpu_side_ports
+ self.bridge.cpu_side_port = (
+ self.get_cache_hierarchy().get_mem_side_port()
+ )
+ self.bridge.ranges = [
+ AddrRange(dev.pio_addr, size=dev.pio_size)
+ for dev in self._off_chip_devices
+ ]
def _setup_pma(self) -> None:
"""Set the PMA devices on each core"""
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51449
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icb6e2e2d2afa377669cc2549d66197e2332f4ed9
Gerrit-Change-Number: 51449
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
