Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52036 )
Change subject: arch,cpu: Refactor PCState construction a little.
......................................................................
arch,cpu: Refactor PCState construction a little.
Make the Addr constructor explicit to avoid implicit/hidden conversions
from Addr.
Also, add a copy constructor to the PCState types, and explicitly enable
the assignment operator.
Change-Id: Ibef17ece7fd06b2f9709c46d118e88a80da0b194
---
M src/cpu/simple_thread.hh
M src/arch/power/insts/branch.cc
M src/arch/x86/pcstate.hh
M src/cpu/thread_context.hh
M src/arch/generic/pcstate.hh
M src/arch/arm/isa.cc
M src/arch/arm/pcstate.hh
M src/arch/arm/faults.cc
M src/cpu/o3/fetch.cc
M src/arch/power/pcstate.hh
M src/arch/riscv/isa/formats/standard.isa
M src/cpu/pred/btb.cc
M src/arch/riscv/faults.cc
13 files changed, 69 insertions(+), 21 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index c82373a..745f9a0 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -798,7 +798,7 @@
}
} else {
// Advance the PC to the IMPLEMENTATION DEFINED reset value
- PCState pc = ArmSystem::resetAddr(tc);
+ PCState pc(ArmSystem::resetAddr(tc));
pc.aarch64(true);
pc.nextAArch64(true);
tc->pcState(pc);
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 3421ce9..158b978 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -618,7 +618,7 @@
ISA::readMiscReg(int misc_reg)
{
CPSR cpsr = 0;
- PCState pc = 0;
+ PCState pc(0);
SCR scr = 0;
if (misc_reg == MISCREG_CPSR) {
diff --git a/src/arch/arm/pcstate.hh b/src/arch/arm/pcstate.hh
index 5bbad26..d2f3cef 100644
--- a/src/arch/arm/pcstate.hh
+++ b/src/arch/arm/pcstate.hh
@@ -91,8 +91,6 @@
bool _stepped = false;
public:
- PCState() {}
-
void
set(Addr val)
{
@@ -100,7 +98,16 @@
npc(val + (thumb() ? 2 : 4));
}
- PCState(Addr val) { set(val); }
+ PCState(const PCState &other) : Base(other),
+ flags(other.flags), nextFlags(other.nextFlags),
+ _itstate(other._itstate), _nextItstate(other._nextItstate),
+ _size(other._size), _illegalExec(other._illegalExec),
+ _debugStep(other._debugStep), _stepped(other._stepped)
+ {}
+ PCState &operator=(const PCState &other) = default;
+
+ PCState() {}
+ explicit PCState(Addr val) { set(val); }
PCStateBase *clone() const override { return new PCState(*this); }
diff --git a/src/arch/generic/pcstate.hh b/src/arch/generic/pcstate.hh
index e66ceda..c48e93d 100644
--- a/src/arch/generic/pcstate.hh
+++ b/src/arch/generic/pcstate.hh
@@ -85,8 +85,12 @@
MicroPC _upc = 0;
MicroPC _nupc = 1;
+ PCStateCommon(const PCStateCommon &other) :
+ _pc(other._pc), _npc(other._npc), _upc(other._upc),
_nupc(other._nupc)
+ {}
+ PCStateCommon &operator=(const PCStateCommon &other) = default;
PCStateCommon() {}
- PCStateCommon(Addr val) { set(val); }
+ explicit PCStateCommon(Addr val) { set(val); }
public:
/**
@@ -209,8 +213,10 @@
npc(val);
}
+ SimplePCState(const SimplePCState &other) : Base(other) {}
+ SimplePCState &operator=(const SimplePCState &other) = default;
SimplePCState() {}
- SimplePCState(Addr val) { set(val); }
+ explicit SimplePCState(Addr val) { set(val); }
bool
branching() const
@@ -263,8 +269,10 @@
nupc(1);
}
+ UPCState(const UPCState &other) : Base(other) {}
+ UPCState &operator=(const UPCState &other) = default;
UPCState() {}
- UPCState(Addr val) { set(val); }
+ explicit UPCState(Addr val) { set(val); }
bool
branching() const
@@ -339,8 +347,12 @@
nnpc(val + 2 * InstWidth);
}
+ DelaySlotPCState(const DelaySlotPCState &other) :
+ Base(other), _nnpc(other._nnpc)
+ {}
+ DelaySlotPCState &operator=(const DelaySlotPCState &other) = default;
DelaySlotPCState() {}
- DelaySlotPCState(Addr val) { set(val); }
+ explicit DelaySlotPCState(Addr val) { set(val); }
bool
branching() const
@@ -434,8 +446,12 @@
nupc(1);
}
+ DelaySlotUPCState(const DelaySlotUPCState &other) :
+ Base(other), _upc(other._upc), _nupc(other._nupc)
+ {}
+ DelaySlotUPCState &operator=(const DelaySlotUPCState &other) = default;
DelaySlotUPCState() {}
- DelaySlotUPCState(Addr val) { set(val); }
+ explicit DelaySlotUPCState(Addr val) { set(val); }
bool
branching() const
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 8992143..861bacd 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -67,7 +67,7 @@
else
addr = tc->pcState().pc() + li;
- return msr.sf ? addr : addr & UINT32_MAX;
+ return PowerISA::PCState(msr.sf ? addr : addr & UINT32_MAX);
}
@@ -115,7 +115,7 @@
else
addr = tc->pcState().pc() + bd;
- return msr.sf ? addr : addr & UINT32_MAX;
+ return PowerISA::PCState(msr.sf ? addr : addr & UINT32_MAX);
}
@@ -160,7 +160,7 @@
{
Msr msr = tc->readIntReg(INTREG_MSR);
Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
- return msr.sf ? addr : addr & UINT32_MAX;
+ return PowerISA::PCState(msr.sf ? addr : addr & UINT32_MAX);
}
diff --git a/src/arch/power/pcstate.hh b/src/arch/power/pcstate.hh
index c46b37e..2b5ddd3 100644
--- a/src/arch/power/pcstate.hh
+++ b/src/arch/power/pcstate.hh
@@ -47,6 +47,12 @@
public:
using GenericISA::SimplePCState<4>::SimplePCState;
+ PCState(const PCState &other) :
+ GenericISA::SimplePCState<4>(other),
+ guestByteOrder(other.guestByteOrder)
+ {}
+ PCState &operator=(const PCState &other) = default;
+
PCStateBase *clone() const override { return new PCState(*this); }
ByteOrder
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index b7fb509..36e2ce9 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -149,7 +149,8 @@
tc->pcState(pcState);
}
-void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+void
+Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
tc->setMiscReg(MISCREG_PRV, PRV_M);
STATUS status = tc->readMiscReg(MISCREG_STATUS);
@@ -160,7 +161,7 @@
// Advance the PC to the implementation-defined reset vector
auto workload = dynamic_cast<Workload *>(tc->getSystemPtr()->workload);
- PCState pc = workload->getEntry();
+ PCState pc(workload->getEntry());
tc->pcState(pc);
}
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index dad2c2b..ce58e54 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -197,7 +197,7 @@
RiscvISA::PCState
%(class_name)s::branchTarget(const RiscvISA::PCState &branchPC) const
{
- return branchPC.pc() + imm;
+ return RiscvISA::PCState(branchPC.pc() + imm);
}
std::string
diff --git a/src/arch/x86/pcstate.hh b/src/arch/x86/pcstate.hh
index 28547f3..c0641ca 100644
--- a/src/arch/x86/pcstate.hh
+++ b/src/arch/x86/pcstate.hh
@@ -50,7 +50,7 @@
class PCState : public GenericISA::UPCState<8>
{
protected:
- typedef GenericISA::UPCState<8> Base;
+ using Base = GenericISA::UPCState<8>;
uint8_t _size;
@@ -64,8 +64,10 @@
_size = 0;
}
+ PCState(const PCState &other) : Base(other), _size(other._size) {}
+ PCState &operator=(const PCState &other) = default;
PCState() {}
- PCState(Addr val) { set(val); }
+ explicit PCState(Addr val) { set(val); }
void
setNPC(Addr val)
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 5bbdc03..cfc3a83 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -120,7 +120,7 @@
for (int i = 0; i < MaxThreads; i++) {
fetchStatus[i] = Idle;
decoder[i] = nullptr;
- pc[i] = 0;
+ pc[i].set(0);
fetchOffset[i] = 0;
macroop[i] = nullptr;
delayedCommit[i] = false;
diff --git a/src/cpu/pred/btb.cc b/src/cpu/pred/btb.cc
index a88ce67..a3950cd 100644
--- a/src/cpu/pred/btb.cc
+++ b/src/cpu/pred/btb.cc
@@ -126,7 +126,7 @@
&& btb[btb_idx].tid == tid) {
return btb[btb_idx].target;
} else {
- return 0;
+ return TheISA::PCState(0);
}
}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index feec42f..ce918be 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -248,7 +248,7 @@
void
clearArchRegs() override
{
- _pcState = 0;
+ _pcState.set(0);
std::fill(intRegs.begin(), intRegs.end(), 0);
std::fill(floatRegs.begin(), floatRegs.end(), 0);
for (auto &vec_reg: vecRegs)
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 3ae8a7f..fee2503 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -226,6 +226,7 @@
virtual TheISA::PCState pcState() const = 0;
virtual void pcState(const TheISA::PCState &val) = 0;
+ void pcState(Addr addr) { pcState(TheISA::PCState(addr)); }
void
setNPC(Addr val)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52036
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibef17ece7fd06b2f9709c46d118e88a80da0b194
Gerrit-Change-Number: 52036
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
