Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/52109 )
Change subject: mem-ruby: Don't conditionalize setting RubySequencer's
pio_response_port
......................................................................
mem-ruby: Don't conditionalize setting RubySequencer's pio_response_port
This was conditioned on the TARGET_ISA being x86 because the code it
replaced was, and that was because the x86 interrupts object had an
extra port that didn't appear for other ISAs. This inconsistency is not
present on either side of this connection, and so we don't need it to be
conditional.
We do, however, need to ensure that the port sends a range change even
if it doesn't have any ranges to send, to satisfy the bookkeeping of the
bus on the other side of the connection. We do that in init, like leaf
devices do.
Change-Id: Idec6f6c5e2cf78b113fb238d0edd2c63d6cd2c23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52109
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/Sequencer.py
2 files changed, 28 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index ff02fde..37c34c5 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -95,6 +95,9 @@
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
for (const auto &response_port : response_ports)
response_port->sendRangeChange();
+ if (gotAddrRanges == 0 && FullSystem) {
+ pioResponsePort.sendRangeChange();
+ }
}
Port &
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 50e8718..703c533 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -122,11 +122,9 @@
do not go though the SLICC protocol so the iobus must be connected
to
the sequencer directly.
"""
- import m5.defines
self.pio_request_port = piobus.cpu_side_ports
self.mem_request_port = piobus.cpu_side_ports
- if m5.defines.buildEnv['TARGET_ISA'] == "x86":
- self.pio_response_port = piobus.mem_side_ports
+ self.pio_response_port = piobus.mem_side_ports
class RubyHTMSequencer(RubySequencer):
type = 'RubyHTMSequencer'
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idec6f6c5e2cf78b113fb238d0edd2c63d6cd2c23
Gerrit-Change-Number: 52109
Gerrit-PatchSet: 4
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Tiago Mück <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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