Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52406 )
Change subject: dev-arm: Ensure all fields of GicV2 are initialized.
......................................................................
dev-arm: Ensure all fields of GicV2 are initialized.
The constructor tried to initialize all values, but in particular missed
intGroup, and may have missed other values as well.
This change adds default initializers to all member variables, and
removes the initializer in the constructor when that version is
redundant. This will ensure that all values are initialized, and make it
obvious when any aren't.
There are some arrays which are initialized by the constructor in a loop
in its body which will now be initialized twice, once with a default
value and once with the loop value. Since this only happens when the
SimObject is constructed and that only happens once during a simulation,
that is a trivial cost to pay for the added safety of knowing the data
structure is initialized.
Change-Id: Ibcd610e40259e46e3cde9b76c7f9ddc816832dfd
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 49 insertions(+), 33 deletions(-)
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index bd780ee..bdf7e95 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -74,14 +74,8 @@
addrRanges{distRange, cpuRange},
distPioDelay(p.dist_pio_delay),
cpuPioDelay(p.cpu_pio_delay), intLatency(p.int_latency),
- enabled(false), haveGem5Extensions(p.gem5_extensions),
- itLines(p.it_lines),
- intEnabled {}, pendingInt {}, activeInt {},
- intPriority {}, intConfig {}, cpuTarget {},
- cpuSgiPending {}, cpuSgiActive {},
- cpuSgiPendingExt {}, cpuSgiActiveExt {},
- cpuPpiPending {}, cpuPpiActive {},
- pendingDelayedInterrupts(0)
+ haveGem5Extensions(p.gem5_extensions),
+ itLines(p.it_lines)
{
for (int x = 0; x < CPU_MAX; x++) {
iccrpr[x] = 0xff;
@@ -99,8 +93,6 @@
}
DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n",
cpuEnabled(0),
cpuEnabled(1));
-
- gem5ExtensionsEnabled = false;
}
GicV2::~GicV2()
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 9e68745..2233622 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -168,13 +168,13 @@
protected:
/** Gic enabled */
- bool enabled;
+ bool enabled = false;
/** Are gem5 extensions available? */
const bool haveGem5Extensions;
/** gem5 many-core extension enabled by driver */
- bool gem5ExtensionsEnabled;
+ bool gem5ExtensionsEnabled = false;
/** Number of itLines enabled */
uint32_t itLines;
@@ -221,7 +221,7 @@
/** GICD_I{S,C}ENABLER{1..31}
* interrupt enable bits for global interrupts
* 1b per interrupt, 32 bits per word, 31 words */
- uint32_t intEnabled[INT_BITS_MAX-1];
+ uint32_t intEnabled[INT_BITS_MAX - 1] = {};
uint32_t&
getIntEnabled(ContextID ctx, uint32_t ix)
@@ -236,7 +236,7 @@
/** GICD_I{S,C}PENDR{1..31}
* interrupt pending bits for global interrupts
* 1b per interrupt, 32 bits per word, 31 words */
- uint32_t pendingInt[INT_BITS_MAX-1];
+ uint32_t pendingInt[INT_BITS_MAX - 1] = {};
uint32_t&
getPendingInt(ContextID ctx, uint32_t ix)
@@ -252,7 +252,7 @@
/** GICD_I{S,C}ACTIVER{1..31}
* interrupt active bits for global interrupts
* 1b per interrupt, 32 bits per word, 31 words */
- uint32_t activeInt[INT_BITS_MAX-1];
+ uint32_t activeInt[INT_BITS_MAX - 1] = {};
uint32_t&
getActiveInt(ContextID ctx, uint32_t ix)
@@ -268,7 +268,7 @@
/** GICD_IGROUPR{1..31}
* interrupt group bits for global interrupts
* 1b per interrupt, 32 bits per word, 31 words */
- uint32_t intGroup[INT_BITS_MAX-1];
+ uint32_t intGroup[INT_BITS_MAX - 1] = {};
uint32_t&
getIntGroup(ContextID ctx, uint32_t ix)
@@ -282,13 +282,13 @@
}
/** read only running priority register, 1 per cpu*/
- uint32_t iccrpr[CPU_MAX];
+ uint32_t iccrpr[CPU_MAX] = {};
/** GICD_IPRIORITYR{8..255}
* an 8 bit priority (lower is higher priority) for each
* of the global (not replicated per CPU) interrupts.
*/
- uint8_t intPriority[GLOBAL_INT_LINES];
+ uint8_t intPriority[GLOBAL_INT_LINES] = {};
uint8_t&
getIntPriority(ContextID ctx, uint32_t ix)
@@ -305,7 +305,7 @@
* GICD_ICFGR{2...63}
* 2 bit per interrupt signaling if it's level or edge sensitive
* and if it is 1:N or N:N */
- uint32_t intConfig[INT_BITS_MAX*2 - 2];
+ uint32_t intConfig[INT_BITS_MAX * 2 - 2] = {};
/**
* Reads the GICD_ICFGRn register.
@@ -328,7 +328,7 @@
/** GICD_ITARGETSR{8..255}
* an 8 bit cpu target id for each global interrupt.
*/
- uint8_t cpuTarget[GLOBAL_INT_LINES];
+ uint8_t cpuTarget[GLOBAL_INT_LINES] = {};
uint8_t
getCpuTarget(ContextID ctx, uint32_t ix) const
@@ -410,35 +410,35 @@
/** GICC_CTLR:
* CPU interface control register
*/
- CTLR cpuControl[CPU_MAX];
+ CTLR cpuControl[CPU_MAX] = {};
/** CPU priority */
- uint8_t cpuPriority[CPU_MAX];
+ uint8_t cpuPriority[CPU_MAX] = {};
uint8_t getCpuPriority(unsigned cpu); // BPR-adjusted priority value
/** Binary point registers */
- uint8_t cpuBpr[CPU_MAX];
+ uint8_t cpuBpr[CPU_MAX] = {};
/** highest interrupt that is interrupting CPU */
- uint32_t cpuHighestInt[CPU_MAX];
+ uint32_t cpuHighestInt[CPU_MAX] = {};
/** One bit per cpu per software interrupt that is pending for each
* possible sgi source. Indexed by SGI number. Each byte in generating
cpu
* id and bits in position is destination id. e.g. 0x4 = CPU 0
generated
* interrupt for CPU 2. */
- uint64_t cpuSgiPending[SGI_MAX];
- uint64_t cpuSgiActive[SGI_MAX];
+ uint64_t cpuSgiPending[SGI_MAX] = {};
+ uint64_t cpuSgiActive[SGI_MAX] = {};
/** SGI pending arrays for gem5 GIC extension mode, which instead keeps
* 16 SGI pending bits for each of the (large number of) CPUs.
*/
- uint32_t cpuSgiPendingExt[CPU_MAX];
- uint32_t cpuSgiActiveExt[CPU_MAX];
+ uint32_t cpuSgiPendingExt[CPU_MAX] = {};
+ uint32_t cpuSgiActiveExt[CPU_MAX] = {};
/** One bit per private peripheral interrupt. Only upper 16 bits
* will be used since PPI interrupts are numberred from 16 to 32 */
- uint32_t cpuPpiPending[CPU_MAX];
- uint32_t cpuPpiActive[CPU_MAX];
+ uint32_t cpuPpiPending[CPU_MAX] = {};
+ uint32_t cpuPpiActive[CPU_MAX] = {};
/** software generated interrupt
* @param data data to decode that indicates which cpus to interrupt
@@ -475,9 +475,9 @@
void postDelayedInt(uint32_t cpu);
void postDelayedFiq(uint32_t cpu);
- EventFunctionWrapper *postIntEvent[CPU_MAX];
- EventFunctionWrapper *postFiqEvent[CPU_MAX];
- int pendingDelayedInterrupts;
+ EventFunctionWrapper *postIntEvent[CPU_MAX] = {};
+ EventFunctionWrapper *postFiqEvent[CPU_MAX] = {};
+ int pendingDelayedInterrupts = 0;
public:
using Params = GicV2Params;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52406
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibcd610e40259e46e3cde9b76c7f9ddc816832dfd
Gerrit-Change-Number: 52406
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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