Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52497 )
Change subject: arch-x86,cpu: Override the int div latency local to x86.
......................................................................
arch-x86,cpu: Override the int div latency local to x86.
Remove the ISA check when selecting the default integer division latency
for O3. Instead, create a parameter which the latency defaults to using
a proxy, and then override that parameter when setting the default
function unit pool in the x86 version of that CPU. The value can still
be overridden if the user wants, but this way it gets its specialized
value within x86 with no ISA check.
Change-Id: I1ef9ee94f4b16aebe03e043df5cdc6167efe6e64
---
M src/arch/x86/X86CPU.py
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
3 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/src/arch/x86/X86CPU.py b/src/arch/x86/X86CPU.py
index 58437ee..6451616 100644
--- a/src/arch/x86/X86CPU.py
+++ b/src/arch/x86/X86CPU.py
@@ -29,6 +29,7 @@
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.FUPool import DefaultFUPool
from m5.objects.X86MMU import X86MMU
from m5.objects.X86LocalApic import X86LocalApic
from m5.objects.X86ISA import X86ISA
@@ -58,3 +59,9 @@
# (it's a side effect of int reg renaming), so they should
# never be the bottleneck here.
numPhysCCRegs = Self.numPhysIntRegs * 5
+
+ # DIV and IDIV instructions in x86 are implemented using a loop which
+ # issues division microops. The latency of these microops should
really be
+ # one (or a small number) cycle each since each of these computes one
bit
+ # of the quotient.
+ fuPool = DefaultFUPool(int_div_lat=1)
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index e9d606e..6d48ce7 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -47,6 +47,10 @@
cxx_header = "cpu/o3/fu_pool.hh"
FUList = VectorParam.FUDesc("list of FU's for this pool")
+ # This latency may need to be specialized for x86. This makes it easy
to
+ # access in subclasses.
+ int_div_lat = Param.Cycles(20, "Default latency for IntDiv")
+
class DefaultFUPool(FUPool):
FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
SIMD_Unit(), PredALU(), WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index 6942f9a..50cb42b 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -39,6 +39,7 @@
from m5.SimObject import SimObject
from m5.defines import buildEnv
from m5.params import *
+from m5.proxy import *
from m5.objects.FuncUnit import *
@@ -48,14 +49,8 @@
class IntMultDiv(FUDesc):
opList = [ OpDesc(opClass='IntMult', opLat=3),
- OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
-
- # DIV and IDIV instructions in x86 are implemented using a loop which
- # issues division microops. The latency of these microops should
really be
- # one (or a small number) cycle each since each of these computes one
bit
- # of the quotient.
- if buildEnv['USE_X86']:
- opList[1].opLat=1
+ OpDesc(opClass='IntDiv', opLat=Parent.int_div_lat,
+ pipelined=False) ]
count=2
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52497
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1ef9ee94f4b16aebe03e043df5cdc6167efe6e64
Gerrit-Change-Number: 52497
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
