Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52491 )
Change subject: misc: Replace TARGET_ISA with USE_${ISA} variables.
......................................................................
misc: Replace TARGET_ISA with USE_${ISA} variables.
The TARGET_ISA variable would let you select one ISA from a list of
possible ISAs. That has now been replaced with USE_ARM, USE_X86, etc,
variables which are boolean on or off. That will allow any number of
ISAs to be enabled or disabled individually. Enabling something other
than exactly one of these will probably prevent you from getting a
working gem5 binary, but those problems are being addressed in other,
parallel change series.
I decided to use the USE_ prefix since it was consistent with most other
on/off variables we have in gem5. One noteable exception is the
BUILD_GPU setting which, you could convincingly argue, is a better
prefix than USE_. Another option would be to use CONFIG_, in
anticipation of using a kconfig style config mechanism in gem5.
It seemed premature to start using a CONFIG_ prefix here, and if we
decide to switch to some other prefix like BUILD_, it should be a
purposeful choice and not something somebody just starts using.
Change-Id: I90fef2835aa4712782e6c1313fbf564d0ed45538
---
M src/cpu/pred/SConscript
M build_opts/MIPS
M configs/learning_gem5/part1/two_level.py
M src/dev/serial/SConscript
M build_opts/RISCV
M src/dev/virtio/SConscript
M src/arch/SConscript
M build_opts/ARM
M configs/example/se.py
M configs/example/apu_se.py
M build_opts/ARM_MESI_Three_Level_HTM
M src/arch/x86/SConsopts
M src/base/SConscript
M src/dev/i2c/SConscript
M src/arch/x86/SConscript
M src/arch/mips/SConscript
M build_opts/NULL
M src/arch/riscv/SConsopts
M build_opts/NULL_MOESI_CMP_directory
M configs/common/ObjectList.py
M tests/configs/o3-timing.py
M src/SConscript
M configs/example/hmc_hello.py
M tests/configs/o3-timing-mt.py
M src/kern/SConscript
M src/arch/sparc/SConscript
M src/arch/generic/SConscript
M src/arch/riscv/SConscript
M build_opts/Garnet_standalone
M src/cpu/o3/SConscript
M src/cpu/minor/SConscript
M src/dev/ps2/SConscript
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M build_opts/VEGA_X86
M build_opts/NULL_MESI_Two_Level
M src/arch/power/SConscript
M configs/learning_gem5/part1/simple.py
M configs/common/Options.py
M build_opts/GCN3_X86
M configs/common/Caches.py
M configs/ruby/Ruby.py
M build_opts/POWER
M configs/example/fs.py
M build_opts/SPARC
M src/dev/SConscript
M src/cpu/o3/probe/SConscript
M src/cpu/trace/SConscript
M configs/learning_gem5/part3/msi_caches.py
M src/arch/mips/SConsopts
M src/arch/x86/kvm/SConscript
M build_opts/ARM_MOESI_hammer
M build_opts/NULL_MOESI_CMP_token
M src/sim/System.py
M src/arch/null/SConsopts
M tests/gem5/cpu_tests/run.py
M src/cpu/simple/probes/SConscript
M src/dev/storage/SConscript
M build_opts/X86_MESI_Two_Level
M src/cpu/o3/FuncUnitConfig.py
M src/python/gem5/runtime.py
M SConstruct
M build_opts/X86_MOESI_AMD_Base
M build_opts/NULL_MOESI_hammer
M src/arch/SConsopts
M src/cpu/SConscript
M src/arch/arm/SConscript
M build_opts/ARM_MESI_Three_Level
M build_opts/X86
M src/arch/arm/SConsopts
M src/arch/power/SConsopts
M configs/learning_gem5/part3/simple_ruby.py
M configs/common/FSConfig.py
M src/arch/sparc/SConsopts
M configs/common/CacheConfig.py
M src/sim/SConscript
M src/mem/SConscript
M src/cpu/kvm/SConscript
M src/cpu/simple/SConscript
78 files changed, 294 insertions(+), 162 deletions(-)
diff --git a/SConstruct b/SConstruct
index 18d24bc..f8626c0 100755
--- a/SConstruct
+++ b/SConstruct
@@ -702,7 +702,21 @@
if env['USE_EFENCE']:
env.Append(LIBS=['efence'])
- if env['KVM_ISA'] != env['TARGET_ISA']:
+ if env['USE_ARM']:
+ isa = 'arm'
+ elif env['USE_MIPS']:
+ isa = 'mips'
+ elif env['USE_POWER']:
+ isa = 'power'
+ elif env['USE_RISCV']:
+ isa = 'riscv'
+ elif env['USE_SPARC']:
+ isa = 'sparc'
+ elif env['USE_X86']:
+ isa = 'x86'
+ elif env['USE_NULL']:
+ isa = 'null'
+ if env['KVM_ISA'] != isa:
env['USE_KVM'] = False
# Save sticky variable settings back to current variables file
diff --git a/build_opts/ARM b/build_opts/ARM
index 5b7da10..5165f3e 100644
--- a/build_opts/ARM
+++ b/build_opts/ARM
@@ -1,2 +1,2 @@
-TARGET_ISA = 'arm'
+USE_ARM = True
PROTOCOL = 'CHI'
diff --git a/build_opts/ARM_MESI_Three_Level
b/build_opts/ARM_MESI_Three_Level
index 2ca31b6..e40d218 100644
--- a/build_opts/ARM_MESI_Three_Level
+++ b/build_opts/ARM_MESI_Three_Level
@@ -1,5 +1,5 @@
# Copyright (c) 2019 ARM Limited
# All rights reserved.
-TARGET_ISA = 'arm'
+USE_ARM = True
PROTOCOL = 'MESI_Three_Level'
diff --git a/build_opts/ARM_MESI_Three_Level_HTM
b/build_opts/ARM_MESI_Three_Level_HTM
index 703398d..aaaf157 100644
--- a/build_opts/ARM_MESI_Three_Level_HTM
+++ b/build_opts/ARM_MESI_Three_Level_HTM
@@ -1,5 +1,5 @@
# Copyright (c) 2019 ARM Limited
# All rights reserved.
-TARGET_ISA = 'arm'
+USE_ARM = True
PROTOCOL = 'MESI_Three_Level_HTM'
diff --git a/build_opts/ARM_MOESI_hammer b/build_opts/ARM_MOESI_hammer
index bd5c63f..cfda4e7 100644
--- a/build_opts/ARM_MOESI_hammer
+++ b/build_opts/ARM_MOESI_hammer
@@ -1,5 +1,5 @@
# Copyright (c) 2019 ARM Limited
# All rights reserved.
-TARGET_ISA = 'arm'
+USE_ARM = True
PROTOCOL = 'MOESI_hammer'
diff --git a/build_opts/GCN3_X86 b/build_opts/GCN3_X86
index b396908..635d9b5 100644
--- a/build_opts/GCN3_X86
+++ b/build_opts/GCN3_X86
@@ -1,4 +1,4 @@
PROTOCOL = 'GPU_VIPER'
-TARGET_ISA = 'x86'
+USE_X86 = True
TARGET_GPU_ISA = 'gcn3'
BUILD_GPU = True
diff --git a/build_opts/Garnet_standalone b/build_opts/Garnet_standalone
index fd730c3..d8d64ff 100644
--- a/build_opts/Garnet_standalone
+++ b/build_opts/Garnet_standalone
@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL = True
PROTOCOL = 'Garnet_standalone'
diff --git a/build_opts/MIPS b/build_opts/MIPS
index 26cb23c..2bd9fb6 100644
--- a/build_opts/MIPS
+++ b/build_opts/MIPS
@@ -1,2 +1,2 @@
-TARGET_ISA = 'mips'
+USE_MIPS = True
PROTOCOL = 'MI_example'
diff --git a/build_opts/NULL b/build_opts/NULL
index b749729..62ba39f 100644
--- a/build_opts/NULL
+++ b/build_opts/NULL
@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL = True
PROTOCOL='MI_example'
diff --git a/build_opts/NULL_MESI_Two_Level b/build_opts/NULL_MESI_Two_Level
index 09147b2..40784e1 100644
--- a/build_opts/NULL_MESI_Two_Level
+++ b/build_opts/NULL_MESI_Two_Level
@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL = True
PROTOCOL = 'MESI_Two_Level'
diff --git a/build_opts/NULL_MOESI_CMP_directory
b/build_opts/NULL_MOESI_CMP_directory
index 466a268..fb36711 100644
--- a/build_opts/NULL_MOESI_CMP_directory
+++ b/build_opts/NULL_MOESI_CMP_directory
@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL = True
PROTOCOL='MOESI_CMP_directory'
diff --git a/build_opts/NULL_MOESI_CMP_token
b/build_opts/NULL_MOESI_CMP_token
index 0cd0305..e594e54 100644
--- a/build_opts/NULL_MOESI_CMP_token
+++ b/build_opts/NULL_MOESI_CMP_token
@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL = True
PROTOCOL='MOESI_CMP_token'
diff --git a/build_opts/NULL_MOESI_hammer b/build_opts/NULL_MOESI_hammer
index 39ebcae..79d7420 100644
--- a/build_opts/NULL_MOESI_hammer
+++ b/build_opts/NULL_MOESI_hammer
@@ -1,2 +1,2 @@
-TARGET_ISA = 'null'
+USE_NULL = True
PROTOCOL='MOESI_hammer'
diff --git a/build_opts/POWER b/build_opts/POWER
index 35772a4..2a5c82a 100644
--- a/build_opts/POWER
+++ b/build_opts/POWER
@@ -1,2 +1,2 @@
-TARGET_ISA = 'power'
+USE_POWER = True
PROTOCOL = 'MI_example'
diff --git a/build_opts/RISCV b/build_opts/RISCV
index 0bd069d..9d9da84 100644
--- a/build_opts/RISCV
+++ b/build_opts/RISCV
@@ -1,2 +1,2 @@
-TARGET_ISA = 'riscv'
+USE_RISCV = True
PROTOCOL = 'MI_example'
diff --git a/build_opts/SPARC b/build_opts/SPARC
index 98acfe2..ccb43b3 100644
--- a/build_opts/SPARC
+++ b/build_opts/SPARC
@@ -1,2 +1,2 @@
-TARGET_ISA = 'sparc'
+USE_SPARC = True
PROTOCOL = 'MI_example'
diff --git a/build_opts/VEGA_X86 b/build_opts/VEGA_X86
index 11e8232..641b3f5 100644
--- a/build_opts/VEGA_X86
+++ b/build_opts/VEGA_X86
@@ -1,4 +1,4 @@
PROTOCOL = 'GPU_VIPER'
-TARGET_ISA = 'x86'
+USE_X86 = True
TARGET_GPU_ISA = 'vega'
BUILD_GPU = True
diff --git a/build_opts/X86 b/build_opts/X86
index 483cf04..f57f490 100644
--- a/build_opts/X86
+++ b/build_opts/X86
@@ -1,2 +1,2 @@
-TARGET_ISA = 'x86'
+USE_X86 = True
PROTOCOL = 'MI_example'
diff --git a/build_opts/X86_MESI_Two_Level b/build_opts/X86_MESI_Two_Level
index 72b200a..93d0105 100644
--- a/build_opts/X86_MESI_Two_Level
+++ b/build_opts/X86_MESI_Two_Level
@@ -1,3 +1,3 @@
-TARGET_ISA = 'x86'
+USE_X86 = True
PROTOCOL = 'MESI_Two_Level'
NUMBER_BITS_PER_SET = '128'
diff --git a/build_opts/X86_MOESI_AMD_Base b/build_opts/X86_MOESI_AMD_Base
index 261bedb..30e4fcc 100644
--- a/build_opts/X86_MOESI_AMD_Base
+++ b/build_opts/X86_MOESI_AMD_Base
@@ -1,2 +1,2 @@
PROTOCOL = 'MOESI_AMD_Base'
-TARGET_ISA = 'x86'
+USE_X86 = True
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index bd68465..3ff5e0f 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -101,7 +101,7 @@
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None
- if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
+ if buildEnv['USE_X86'] or buildEnv['USE_RISCV']:
walk_cache_class = PageTableWalkerCache
# Set the cache line size of the system
@@ -174,7 +174,8 @@
# on these names. For simplicity, we would advise configuring
# it to use this naming scheme; if this isn't possible, change
# the names below.
- if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
+ if buildEnv['USE_X86'] or buildEnv['USE_ARM'] or \
+ buildEnv['USE_RISCV']:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 1468b95..b3988c0 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -90,7 +90,7 @@
tgts_per_mshr = 12
# the x86 table walker actually writes to the table-walker cache
- if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
+ if buildEnv['USE_X86'] or buildEnv['USE_RISCV']:
is_read_only = False
else:
is_read_only = True
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index efb0af6..29b46f6 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -39,23 +39,30 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
+import m5.defines
from m5.objects import *
from m5.util import *
from common.Benchmarks import *
from common import ObjectList
# Populate to reflect supported os types per target ISA
-os_types = { 'mips' : [ 'linux' ],
- 'riscv' : [ 'linux' ], # TODO that's a lie
- 'sparc' : [ 'linux' ],
- 'x86' : [ 'linux' ],
- 'arm' : [ 'linux',
- 'android-gingerbread',
- 'android-ics',
- 'android-jellybean',
- 'android-kitkat',
- 'android-nougat', ],
- }
+if m5.defines.buildEnv['USE_ARM']:
+ os_types = [ 'linux',
+ 'android-gingerbread',
+ 'android-ics',
+ 'android-jellybean',
+ 'android-kitkat',
+ 'android-nougat', ]
+elif m5.defines.buildEnv['USE_MIPS']:
+ os_types = [ 'linux' ]
+elif m5.defines.buildEnv['USE_POWER']:
+ os_types = [ 'linux' ]
+elif m5.defines.buildEnv['USE_RISCV']:
+ os_types = [ 'linux' ] # TODO that's a lie
+elif m5.defines.buildEnv['USE_SPARC']:
+ os_types = [ 'linux' ]
+elif m5.defines.buildEnv['USE_X86']:
+ os_types = [ 'linux' ]
class CowIdeDisk(IdeDisk):
image = CowDiskImage(child=RawDiskImage(read_only=True),
diff --git a/configs/common/ObjectList.py b/configs/common/ObjectList.py
index 685dbc1..8e0f67f 100644
--- a/configs/common/ObjectList.py
+++ b/configs/common/ObjectList.py
@@ -134,7 +134,21 @@
from m5.defines import buildEnv
from importlib import import_module
- for package in [ "generic", buildEnv['TARGET_ISA']]:
+ if buildEnv['USE_ARM']:
+ isa = 'arm'
+ elif buildEnv['USE_MIPS']:
+ isa = 'mips'
+ elif buildEnv['USE_POWER']:
+ isa = 'power'
+ elif buildEnv['USE_RISCV']:
+ isa = 'riscv'
+ elif buildEnv['USE_SPARC']:
+ isa = 'sparc'
+ elif buildEnv['USE_X86']:
+ isa = 'x86'
+ elif buildEnv['USE_NULL']:
+ isa = 'null'
+ for package in [ "generic", isa ]:
try:
package = import_module(".cores." + package,
package=__name__.rpartition('.')[0])
diff --git a/configs/common/Options.py b/configs/common/Options.py
index a63cc7b..2b81490 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -467,7 +467,7 @@
# System options
parser.add_argument("--kernel", action="store", type=str)
parser.add_argument("--os-type", action="store",
- choices=os_types[str(buildEnv['TARGET_ISA'])],
+ choices=os_types,
default="linux",
help="Specifies type of OS to boot")
parser.add_argument("--script", action="store", type=str)
@@ -476,7 +476,7 @@
help="Stores changed frame buffers from the VNC server to
compressed "
"files in the gem5 output directory")
- if buildEnv['TARGET_ISA'] == "arm":
+ if buildEnv['USE_ARM']:
parser.add_argument(
"--bare-metal", action="store_true",
help="Provide the raw system without the linux specific bits")
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 29ceddb..6b6600b 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -544,7 +544,7 @@
if fast_forward:
have_kvm_support = 'BaseKvmCPU' in globals()
- if have_kvm_support and buildEnv['TARGET_ISA'] == "x86":
+ if have_kvm_support and buildEnv['USE_X86']:
system.vm = KvmVM()
for i in range(len(host_cpu.workload)):
host_cpu.workload[i].useArchPT = True
@@ -580,7 +580,7 @@
system.cpu[i].dcache_port = ruby_port.in_ports
ruby_port.mem_request_port = system.piobus.cpu_side_ports
- if buildEnv['TARGET_ISA'] == "x86":
+ if buildEnv['USE_X86']:
system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
system.cpu[i].interrupts[0].int_requestor = \
system.piobus.cpu_side_ports
diff --git a/configs/example/fs.py b/configs/example/fs.py
index a39d2b3..2b9b404 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -76,17 +76,17 @@
def build_test_system(np):
cmdline = cmd_line_template()
- if buildEnv['TARGET_ISA'] == "mips":
+ if buildEnv['USE_MIPS']:
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0],
cmdline=cmdline)
- elif buildEnv['TARGET_ISA'] == "sparc":
+ elif buildEnv['USE_SPARC']:
test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
- elif buildEnv['TARGET_ISA'] == "riscv":
+ elif buildEnv['USE_RISCV']:
test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0],
cmdline=cmdline)
- elif buildEnv['TARGET_ISA'] == "x86":
+ elif buildEnv['USE_X86']:
test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], args.ruby,
cmdline=cmdline)
- elif buildEnv['TARGET_ISA'] == "arm":
+ elif buildEnv['USE_ARM']:
test_sys = makeArmSystem(
test_mem_mode,
args.machine_type,
@@ -103,7 +103,7 @@
if args.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
- fatal("Incapable of building %s full system!",
buildEnv['TARGET_ISA'])
+ fatal("Incapable of building full system!")
# Set the cache line size for the entire system
test_sys.cache_line_size = args.cacheline_size
@@ -123,7 +123,7 @@
voltage_domain =
test_sys.cpu_voltage_domain)
- if buildEnv['TARGET_ISA'] == 'riscv':
+ if buildEnv['USE_RISCV']:
test_sys.workload.bootloader = args.kernel
elif args.kernel is not None:
test_sys.workload.object_file = binary(args.kernel)
@@ -233,14 +233,14 @@
DriveMemClass = SimpleMemory
cmdline = cmd_line_template()
- if buildEnv['TARGET_ISA'] == 'mips':
+ if buildEnv['USE_MIPS']:
drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1],
cmdline=cmdline)
- elif buildEnv['TARGET_ISA'] == 'sparc':
+ elif buildEnv['USE_SPARC']:
drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
- elif buildEnv['TARGET_ISA'] == 'x86':
+ elif buildEnv['USE_X86']:
drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
cmdline=cmdline)
- elif buildEnv['TARGET_ISA'] == 'arm':
+ elif buildEnv['USE_ARM']:
drive_sys = makeArmSystem(drive_mem_mode, args.machine_type, np,
bm[1], args.dtb_filename,
cmdline=cmdline)
@@ -358,8 +358,7 @@
if args.frame_capture:
VncServer.frame_capture = True
-if buildEnv['TARGET_ISA'] == "arm" and not args.bare_metal \
- and not args.dtb_filename:
+if buildEnv['USE_ARM'] and not args.bare_metal and not args.dtb_filename:
if args.machine_type not in ["VExpress_GEM5",
"VExpress_GEM5_V1",
"VExpress_GEM5_V2",
diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py
index 8b3638f..c3bd491 100644
--- a/configs/example/hmc_hello.py
+++ b/configs/example/hmc_hello.py
@@ -66,7 +66,18 @@
# functional-only port to allow the system to read and write memory.
system.system_port = system.membus.slave
# get ISA for the binary to run.
-isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+if m5.defines.buildEnv['USE_ARM']:
+ isa = 'arm'
+elif m5.defines.buildEnv['USE_MIPS']:
+ isa = 'mips'
+elif m5.defines.buildEnv['USE_POWER']:
+ isa = 'power'
+elif m5.defines.buildEnv['USE_RISCV']:
+ isa = 'riscv'
+elif m5.defines.buildEnv['USE_SPARC']:
+ isa = 'sparc'
+elif m5.defines.buildEnv['USE_X86']:
+ isa = 'x86'
# run 'hello' and use the compiled ISA to find the binary
binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
# create a process for a simple "Hello World" application
diff --git a/configs/example/se.py b/configs/example/se.py
index 863f957..b55fe13 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -136,17 +136,17 @@
for app in apps:
try:
- if buildEnv['TARGET_ISA'] == 'arm':
+ if buildEnv['USE_ARM']:
exec("workload = %s('arm_%s', 'linux', '%s')" % (
app, args.arm_iset, args.spec_input))
else:
+ # TARGET_ISA has been removed, but this is missing a ], so
it
+ # has incorrect syntax and wasn't being used anyway.
exec("workload
= %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
app, args.spec_input))
multiprocesses.append(workload.makeProcess())
except:
- print("Unable to find workload for %s: %s" %
- (buildEnv['TARGET_ISA'], app),
- file=sys.stderr)
+ print("Unable to find workload for %s" % app, file=sys.stderr)
sys.exit(1)
elif args.cmd:
multiprocesses, numThreads = get_processes(args)
@@ -198,7 +198,7 @@
cpu.clk_domain = system.cpu_clk_domain
if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass):
- if buildEnv['TARGET_ISA'] == 'x86':
+ if buildEnv['USE_X86']:
system.kvm_vm = KvmVM()
for process in multiprocesses:
process.useArchPT = True
diff --git a/configs/learning_gem5/part1/simple.py
b/configs/learning_gem5/part1/simple.py
index 235165b..3528bea 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -67,7 +67,7 @@
# For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+if m5.defines.buildEnv['USE_X86']:
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
@@ -82,7 +82,18 @@
system.system_port = system.membus.cpu_side_ports
# get ISA for the binary to run.
-isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+if m5.defines.buildEnv['USE_ARM']:
+ isa = 'arm'
+elif m5.defines.buildEnv['USE_MIPS']:
+ isa = 'mips'
+elif m5.defines.buildEnv['USE_POWER']:
+ isa = 'power'
+elif m5.defines.buildEnv['USE_RISCV']:
+ isa = 'riscv'
+elif m5.defines.buildEnv['USE_SPARC']:
+ isa = 'sparc'
+elif m5.defines.buildEnv['USE_X86']:
+ isa = 'x86'
# Default to running 'hello', use the compiled ISA to find the binary
# grab the specific path to the binary
diff --git a/configs/learning_gem5/part1/two_level.py
b/configs/learning_gem5/part1/two_level.py
index 591be0c..70471ce 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -53,7 +53,18 @@
from common import SimpleOpts
# get ISA for the default binary to run. This is mostly for simple testing
-isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+if m5.defines.buildEnv['USE_ARM']:
+ isa = 'arm'
+elif m5.defines.buildEnv['USE_MIPS']:
+ isa = 'mips'
+elif m5.defines.buildEnv['USE_POWER']:
+ isa = 'power'
+elif m5.defines.buildEnv['USE_RISCV']:
+ isa = 'riscv'
+elif m5.defines.buildEnv['USE_SPARC']:
+ isa = 'sparc'
+elif m5.defines.buildEnv['USE_X86']:
+ isa = 'x86'
# Default to running 'hello', use the compiled ISA to find the binary
# grab the specific path to the binary
@@ -112,7 +123,7 @@
# For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+if m5.defines.buildEnv['USE_X86']:
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
diff --git a/configs/learning_gem5/part3/msi_caches.py
b/configs/learning_gem5/part3/msi_caches.py
index 1614c46..c8e6d8e 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -143,7 +143,7 @@
3. The local exclusive monitor in ARM systems
"""
if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+ buildEnv['USE_X86'] or buildEnv['USE_ARM']:
return True
return False
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py
b/configs/learning_gem5/part3/ruby_caches_MI_example.py
index 0406829..2e0f377 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -140,7 +140,7 @@
3. The local exclusive monitor in ARM systems
"""
if type(cpu) is DerivO3CPU or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+ buildEnv['USE_X86'] or buildEnv['USE_ARM']:
return True
return False
diff --git a/configs/learning_gem5/part3/simple_ruby.py
b/configs/learning_gem5/part3/simple_ruby.py
index 2e65ebd..76d259d 100644
--- a/configs/learning_gem5/part3/simple_ruby.py
+++ b/configs/learning_gem5/part3/simple_ruby.py
@@ -79,7 +79,18 @@
system.caches.setup(system, system.cpu, [system.mem_ctrl])
# get ISA for the binary to run.
-isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+if m5.defines.buildEnv['USE_ARM']:
+ isa = 'arm'
+elif m5.defines.buildEnv['USE_MIPS']:
+ isa = 'mips'
+elif m5.defines.buildEnv['USE_POWER']:
+ isa = 'power'
+elif m5.defines.buildEnv['USE_RISCV']:
+ isa = 'riscv'
+elif m5.defines.buildEnv['USE_SPARC']:
+ isa = 'sparc'
+elif m5.defines.buildEnv['USE_X86']:
+ isa = 'x86'
# Run application and use the compiled ISA to find the binary
# grab the specific path to the binary
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 16bb184..efb6b8d 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -277,6 +277,6 @@
# 2. The x86 mwait instruction is built on top of coherence
invalidations
# 3. The local exclusive monitor in ARM systems
if options.cpu_type == "DerivO3CPU" or \
- buildEnv['TARGET_ISA'] in ('x86', 'arm'):
+ buildEnv['USE_X86'] or buildEnv['USE_ARM']:
return True
return False
diff --git a/src/SConscript b/src/SConscript
index 25ac888..68fcd69 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -471,9 +471,21 @@
env.ConfigFile(opt)
def makeTheISA(source, target, env):
- isas = sorted(set(env.Split('${ALL_ISAS}')))
- target_isa = env['TARGET_ISA']
- is_null_isa = '1' if (target_isa.lower() == 'null') else '0'
+ if env['USE_ARM']:
+ target_isa = 'arm'
+ elif env['USE_MIPS']:
+ target_isa = 'mips'
+ elif env['USE_POWER']:
+ target_isa = 'power'
+ elif env['USE_RISCV']:
+ target_isa = 'riscv'
+ elif env['USE_SPARC']:
+ target_isa = 'sparc'
+ elif env['USE_X86']:
+ target_isa = 'x86'
+ elif env['USE_NULL']:
+ target_isa = 'null'
+ is_null_isa = '1' if (target_isa == 'null') else '0'
def namespace(isa):
return isa[0].upper() + isa[1:].lower() + 'ISA'
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 3f65343..cc003a3 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -51,11 +51,31 @@
# ISA "switch header" generation.
#
# Auto-generate arch headers that include the right ISA-specific
-# header based on the setting of TARGET_ISA setting.
+# header based on the USE_${ISA} setting.
#
#################################################################
-env.TagImplies(env.subst('${TARGET_ISA} isa'), 'gem5 lib')
+if env['USE_ARM']:
+ env.TagImplies('arm isa', 'gem5 lib')
+ isa = 'arm'
+elif env['USE_MIPS']:
+ env.TagImplies('mips isa', 'gem5 lib')
+ isa = 'mips'
+elif env['USE_POWER']:
+ env.TagImplies('power isa', 'gem5 lib')
+ isa = 'power'
+elif env['USE_RISCV']:
+ env.TagImplies('riscv isa', 'gem5 lib')
+ isa = 'riscv'
+elif env['USE_SPARC']:
+ env.TagImplies('sparc isa', 'gem5 lib')
+ isa = 'sparc'
+elif env['USE_X86']:
+ env.TagImplies('x86 isa', 'gem5 lib')
+ isa = 'x86'
+elif env['USE_NULL']:
+ env.TagImplies('null isa', 'gem5 lib')
+ isa = 'null'
env.SwitchingHeaders(
Split('''
@@ -64,7 +84,7 @@
pcstate.hh
vecregs.hh
'''),
- env.subst('${TARGET_ISA}'))
+ isa)
amdgpu_isa = ['gcn3', 'vega']
diff --git a/src/arch/SConsopts b/src/arch/SConsopts
index 38b02f5..8e6fd8d 100644
--- a/src/arch/SConsopts
+++ b/src/arch/SConsopts
@@ -27,11 +27,9 @@
def add_isa_lists():
sticky_vars.AddVariables(
- EnumVariable('TARGET_ISA', 'Target ISA', 'null',
- sorted(set(main.Split('${ALL_ISAS}')))),
EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'gcn3',
sorted(set(main.Split('${ALL_GPU_ISAS}')))),
)
AfterSConsopts(add_isa_lists)
-export_vars.extend(['TARGET_ISA', 'TARGET_GPU_ISA'])
+export_vars.extend(['TARGET_GPU_ISA'])
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 756e824..726e37b 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -105,7 +105,7 @@
SimObject('ArmPMU.py', tags='arm isa')
SimObject('ArmCPU.py', tags='arm isa')
-if env['TARGET_ISA'] == 'arm':
+if env['USE_ARM']:
SimObject('AtomicSimpleCPU.py', tags='arm isa')
SimObject('TimingSimpleCPU.py', tags='arm isa')
SimObject('NonCachingSimpleCPU.py', tags='arm isa')
diff --git a/src/arch/arm/SConsopts b/src/arch/arm/SConsopts
index c284f2c..5c8b923 100644
--- a/src/arch/arm/SConsopts
+++ b/src/arch/arm/SConsopts
@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2007-2008 The Florida State University
-# All rights reserved.
+# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-main.Append(ALL_ISAS=['arm'])
+sticky_vars.Add(BoolVariable('USE_ARM', 'Enable ARM ISA support', False))
+export_vars.append('USE_ARM')
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index 70bb2de..5c22498 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -50,7 +50,7 @@
"Page table walker state machine debugging")
DebugFlag('TLB')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
Source('decoder.cc')
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index e252ab0..7259078 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -50,7 +50,7 @@
SimObject('MipsTLB.py', tags='mips isa')
SimObject('MipsCPU.py', tags='mips isa')
-if env['TARGET_ISA'] == 'mips':
+if env['USE_MIPS']:
SimObject('AtomicSimpleCPU.py', tags='mips isa')
SimObject('TimingSimpleCPU.py', tags='mips isa')
SimObject('NonCachingSimpleCPU.py', tags='mips isa')
diff --git a/src/arch/mips/SConsopts b/src/arch/mips/SConsopts
index 58240c1..5450c01 100644
--- a/src/arch/mips/SConsopts
+++ b/src/arch/mips/SConsopts
@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
+# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-main.Append(ALL_ISAS=['mips'])
+sticky_vars.Add(BoolVariable('USE_MIPS', 'Enable MIPS ISA support', False))
+export_vars.append('USE_MIPS')
diff --git a/src/arch/null/SConsopts b/src/arch/null/SConsopts
index 6355ce3..2832833 100644
--- a/src/arch/null/SConsopts
+++ b/src/arch/null/SConsopts
@@ -1,16 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2013 ARM Limited
-# All rights reserved
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
+# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -36,5 +24,5 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-main.Append(ALL_ISAS=['null'])
+sticky_vars.Add(BoolVariable('USE_NULL', 'Enable NULL ISA support', False))
+export_vars.append('USE_NULL')
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index b8fe596..d38aae7 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -53,7 +53,7 @@
SimObject('PowerTLB.py', tags='power isa')
SimObject('PowerCPU.py', tags='power isa')
-if env['TARGET_ISA'] == 'power':
+if env['USE_POWER']:
SimObject('AtomicSimpleCPU.py', tags='power isa')
SimObject('TimingSimpleCPU.py', tags='power isa')
SimObject('NonCachingSimpleCPU.py', tags='power isa')
diff --git a/src/arch/power/SConsopts b/src/arch/power/SConsopts
index cb136fe..4c79c53 100644
--- a/src/arch/power/SConsopts
+++ b/src/arch/power/SConsopts
@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2009 The University of Edinburgh
-# All rights reserved.
+# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-main.Append(ALL_ISAS=['power'])
+sticky_vars.Add(BoolVariable('USE_POWER', 'Enable POWER ISA support',
False))
+export_vars.append('USE_POWER')
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 7f5848e..eee1d43 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -70,7 +70,7 @@
SimObject('RiscvTLB.py', tags='riscv isa')
SimObject('RiscvCPU.py', tags='riscv isa')
-if env['TARGET_ISA'] == 'riscv':
+if env['USE_RISCV']:
SimObject('AtomicSimpleCPU.py', tags='riscv isa')
SimObject('TimingSimpleCPU.py', tags='riscv isa')
SimObject('NonCachingSimpleCPU.py', tags='riscv isa')
diff --git a/src/arch/riscv/SConsopts b/src/arch/riscv/SConsopts
index 76713ee..d67b793 100644
--- a/src/arch/riscv/SConsopts
+++ b/src/arch/riscv/SConsopts
@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
+# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-main.Append(ALL_ISAS=['riscv'])
+sticky_vars.Add(BoolVariable('USE_RISCV', 'Enable RISC-V ISA support',
False))
+export_vars.append('USE_RISCV')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 6560b83..500cda6 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -52,7 +52,7 @@
SimObject('SparcTLB.py', tags='sparc isa')
SimObject('SparcCPU.py', tags='sparc isa')
-if env['TARGET_ISA'] == 'sparc':
+if env['USE_SPARC']:
SimObject('AtomicSimpleCPU.py', tags='sparc isa')
SimObject('TimingSimpleCPU.py', tags='sparc isa')
SimObject('NonCachingSimpleCPU.py', tags='sparc isa')
diff --git a/src/arch/sparc/SConsopts b/src/arch/sparc/SConsopts
index 48fb4a6..6bb7599 100644
--- a/src/arch/sparc/SConsopts
+++ b/src/arch/sparc/SConsopts
@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
+# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-main.Append(ALL_ISAS=['sparc'])
+sticky_vars.Add(BoolVariable('USE_SPARC', 'Enable SPARC ISA support',
False))
+export_vars.append('USE_SPARC')
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index b15eb7f..ec66482 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -70,7 +70,7 @@
SimObject('X86TLB.py', tags='x86 isa')
SimObject('X86CPU.py', tags='x86 isa')
-if env['TARGET_ISA'] == 'x86':
+if env['USE_X86']:
SimObject('AtomicSimpleCPU.py', tags='x86 isa')
SimObject('TimingSimpleCPU.py', tags='x86 isa')
SimObject('NonCachingSimpleCPU.py', tags='x86 isa')
diff --git a/src/arch/x86/SConsopts b/src/arch/x86/SConsopts
index 93dff8c..4a27a53 100644
--- a/src/arch/x86/SConsopts
+++ b/src/arch/x86/SConsopts
@@ -1,7 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2007 The Hewlett-Packard Development Company
-# All rights reserved.
+# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -27,5 +24,5 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-main.Append(ALL_ISAS=['x86'])
+sticky_vars.Add(BoolVariable('USE_X86', 'Enable X86 ISA support', False))
+export_vars.append('USE_X86')
diff --git a/src/arch/x86/kvm/SConscript b/src/arch/x86/kvm/SConscript
index 4518f72..56f85ad 100644
--- a/src/arch/x86/kvm/SConscript
+++ b/src/arch/x86/kvm/SConscript
@@ -37,7 +37,7 @@
Import('*')
-if not env['USE_KVM'] or env['TARGET_ISA'] != env['KVM_ISA']:
+if not env['USE_KVM'] or env['KVM_ISA'] != 'x86':
Return()
SimObject('X86KvmCPU.py', tags='x86 isa')
diff --git a/src/base/SConscript b/src/base/SConscript
index bdc8932..6807b25 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -70,7 +70,7 @@
GTest('pixel.test', 'pixel.test.cc', 'pixel.cc')
Source('pollevent.cc')
Source('random.cc')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
Source('remote_gdb.cc')
Source('socket.cc')
GTest('socket.test', 'socket.test.cc', 'socket.cc')
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 0aaca12..cc56aeb 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -85,7 +85,7 @@
SimObject('FuncUnit.py')
SimObject('StaticInstFlags.py')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
# Only build the protobuf instructions tracer if we have protobuf support.
diff --git a/src/cpu/kvm/SConscript b/src/cpu/kvm/SConscript
index 1b90408..54ff52f 100644
--- a/src/cpu/kvm/SConscript
+++ b/src/cpu/kvm/SConscript
@@ -37,7 +37,21 @@
Import('*')
-if not env['USE_KVM'] or env['TARGET_ISA'] != env['KVM_ISA']:
+if env['USE_ARM']:
+ isa = 'arm'
+elif env['USE_MIPS']:
+ isa = 'mips'
+elif env['USE_POWER']:
+ isa = 'power'
+elif env['USE_RISCV']:
+ isa = 'riscv'
+elif env['USE_SPARC']:
+ isa = 'sparc'
+elif env['USE_X86']:
+ isa = 'x86'
+elif env['USE_NULL']:
+ isa = 'null'
+if not env['USE_KVM'] or isa != env['KVM_ISA']:
Return()
SimObject('KvmVM.py')
diff --git a/src/cpu/minor/SConscript b/src/cpu/minor/SConscript
index 5f51770..2aedad7 100644
--- a/src/cpu/minor/SConscript
+++ b/src/cpu/minor/SConscript
@@ -40,7 +40,7 @@
Import('*')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
SimObject('BaseMinorCPU.py')
Source('activity.cc')
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index ccbefc5..6942f9a 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -54,7 +54,7 @@
# issues division microops. The latency of these microops should
really be
# one (or a small number) cycle each since each of these computes one
bit
# of the quotient.
- if buildEnv['TARGET_ISA'] in ('x86'):
+ if buildEnv['USE_X86']:
opList[1].opLat=1
count=2
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index 5cceadb..404d7a8 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -30,7 +30,7 @@
Import('*')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
SimObject('FUPool.py')
SimObject('FuncUnitConfig.py')
SimObject('BaseO3CPU.py')
diff --git a/src/cpu/o3/probe/SConscript b/src/cpu/o3/probe/SConscript
index c8b3be2..b41e932 100644
--- a/src/cpu/o3/probe/SConscript
+++ b/src/cpu/o3/probe/SConscript
@@ -37,7 +37,7 @@
Import('*')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
SimObject('SimpleTrace.py')
Source('simple_trace.cc')
DebugFlag('SimpleTrace')
diff --git a/src/cpu/pred/SConscript b/src/cpu/pred/SConscript
index fcc32e9..9bc687d 100644
--- a/src/cpu/pred/SConscript
+++ b/src/cpu/pred/SConscript
@@ -28,7 +28,7 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
SimObject('BranchPredictor.py')
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index 3291f0b..2862a9a 100644
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -28,7 +28,7 @@
Import('*')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
SimObject('BaseAtomicSimpleCPU.py')
Source('atomic.cc')
diff --git a/src/cpu/simple/probes/SConscript
b/src/cpu/simple/probes/SConscript
index eb2ff75..a16682a 100644
--- a/src/cpu/simple/probes/SConscript
+++ b/src/cpu/simple/probes/SConscript
@@ -28,6 +28,6 @@
Import('*')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
SimObject('SimPoint.py')
Source('simpoint.cc')
diff --git a/src/cpu/trace/SConscript b/src/cpu/trace/SConscript
index aa450b1..c00160c 100644
--- a/src/cpu/trace/SConscript
+++ b/src/cpu/trace/SConscript
@@ -1,6 +1,6 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
# Only build TraceCPU if we have support for protobuf as TraceCPU relies
on it
diff --git a/src/dev/SConscript b/src/dev/SConscript
index e86e48b..77f2109 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -43,7 +43,7 @@
SimObject('Platform.py')
Source('platform.cc')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
SimObject('BadDevice.py')
diff --git a/src/dev/i2c/SConscript b/src/dev/i2c/SConscript
index f20a6a2..9e6691c 100644
--- a/src/dev/i2c/SConscript
+++ b/src/dev/i2c/SConscript
@@ -37,7 +37,7 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
SimObject('I2C.py')
diff --git a/src/dev/ps2/SConscript b/src/dev/ps2/SConscript
index b6fc482..28ce713 100644
--- a/src/dev/ps2/SConscript
+++ b/src/dev/ps2/SConscript
@@ -37,7 +37,7 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
SimObject('PS2.py')
diff --git a/src/dev/serial/SConscript b/src/dev/serial/SConscript
index 309020b..3e5130b 100644
--- a/src/dev/serial/SConscript
+++ b/src/dev/serial/SConscript
@@ -40,7 +40,7 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
SimObject('Serial.py')
diff --git a/src/dev/storage/SConscript b/src/dev/storage/SConscript
index d615435..aed6561 100644
--- a/src/dev/storage/SConscript
+++ b/src/dev/storage/SConscript
@@ -40,7 +40,7 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
# Controllers
diff --git a/src/dev/virtio/SConscript b/src/dev/virtio/SConscript
index a22f35e..a4c07d8 100644
--- a/src/dev/virtio/SConscript
+++ b/src/dev/virtio/SConscript
@@ -37,7 +37,7 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
SimObject('VirtIO.py')
diff --git a/src/kern/SConscript b/src/kern/SConscript
index 3d5872b..757fb45 100644
--- a/src/kern/SConscript
+++ b/src/kern/SConscript
@@ -28,7 +28,7 @@
Import('*')
-if env['TARGET_ISA'] == 'null':
+if env['USE_NULL']:
Return()
Source('linux/events.cc')
diff --git a/src/mem/SConscript b/src/mem/SConscript
index ddf6fee..861eaeb 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -90,7 +90,7 @@
GTest('translation_gen.test', 'translation_gen.test.cc')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
Source('translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
diff --git a/src/python/gem5/runtime.py b/src/python/gem5/runtime.py
index 9e1f607..924da67 100644
--- a/src/python/gem5/runtime.py
+++ b/src/python/gem5/runtime.py
@@ -50,10 +50,23 @@
"riscv": ISA.RISCV,
}
- isa_str = str(buildEnv["TARGET_ISA"]).lower()
+ if buildEnv['USE_ARM']:
+ isa_str = 'arm'
+ elif buildEnv['USE_MIPS']:
+ isa_str = 'mips'
+ elif buildEnv['USE_POWER']:
+ isa_str = 'power'
+ elif buildEnv['USE_RISCV']:
+ isa_str = 'riscv'
+ elif buildEnv['USE_SPARC']:
+ isa_str = 'sparc'
+ elif buildEnv['USE_X86']:
+ isa_str = 'x86'
+ elif buildEnv['USE_NULL']:
+ isa_str = 'null'
if isa_str not in isa_map.keys():
raise NotImplementedError(
- "ISA '" + buildEnv["TARGET_ISA"] + "' not recognized."
+ "ISA '" + isa_str + "' not recognized."
)
return isa_map[isa_str]
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 449ded8..5b9129c 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -96,7 +96,7 @@
GTest('serialize.test', 'serialize.test.cc', with_tag('gem5 serialize'))
GTest('serialize_handlers.test', 'serialize_handlers.test.cc')
-if env['TARGET_ISA'] != 'null':
+if not env['USE_NULL']:
SimObject('InstTracer.py')
SimObject('Process.py')
Source('faults.cc')
diff --git a/src/sim/System.py b/src/sim/System.py
index 596e25c..85e5a09 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -124,8 +124,7 @@
# SE mode doesn't use the ISA System subclasses, and so we need to set
an
# ISA specific value in this class directly.
- m5ops_base = Param.Addr(
- 0xffff0000 if buildEnv['TARGET_ISA'] == 'x86' else 0,
+ m5ops_base = Param.Addr(0xffff0000 if buildEnv['USE_X86'] else 0,
"Base of the 64KiB PA range used for memory-mapped m5ops. Set to
0 "
"to disable.")
diff --git a/tests/configs/o3-timing-mt.py b/tests/configs/o3-timing-mt.py
index 5c98f33..9648e06 100644
--- a/tests/configs/o3-timing-mt.py
+++ b/tests/configs/o3-timing-mt.py
@@ -45,7 +45,7 @@
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
-if buildEnv['TARGET_ISA'] == "arm":
+if buildEnv['USE_ARM']:
root = ArmSESystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_threads=2).create_root()
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 3788df9..d1c9500 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -45,7 +45,7 @@
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
-if buildEnv['TARGET_ISA'] == "arm":
+if buildEnv['USE_ARM']:
root = ArmSESystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()
else:
diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py
index f6a1cf6..c6cf5ee 100644
--- a/tests/gem5/cpu_tests/run.py
+++ b/tests/gem5/cpu_tests/run.py
@@ -92,7 +92,7 @@
class MySimpleMemory(SimpleMemory):
latency = '1ns'
-if buildEnv['TARGET_ISA'] == 'x86':
+if buildEnv['USE_X86']:
valid_cpu = {'AtomicSimpleCPU': AtomicSimpleCPU,
'TimingSimpleCPU': TimingSimpleCPU,
'DerivO3CPU': DerivO3CPU
@@ -150,7 +150,7 @@
system.l2cache.connectMemSideBus(system.membus)
system.cpu.createInterruptController()
-if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+if m5.defines.buildEnv['USE_X86']:
system.cpu.interrupts[0].pio = system.membus.master
system.cpu.interrupts[0].int_master = system.membus.slave
system.cpu.interrupts[0].int_slave = system.membus.master
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52491
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I90fef2835aa4712782e6c1313fbf564d0ed45538
Gerrit-Change-Number: 52491
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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