Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/52583 )
Change subject: configs: Replace connectAllPorts with connectCachedPorts
......................................................................
configs: Replace connectAllPorts with connectCachedPorts
Uncached ports are not used in Arm configs (X86 only [1])
[1]: https://github.com/gem5/gem5/blob/stable/src/cpu/BaseCPU.py#L181
Change-Id: I0f71f605ef73d9adc418414c891569bc475b2587
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52583
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M configs/example/arm/devices.py
1 file changed, 20 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index f729fb5..788c268 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -150,7 +150,7 @@
self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
self.l2 = self._l2_type()
for cpu in self.cpus:
- cpu.connectAllPorts(self.toL2Bus)
+ cpu.connectCachedPorts(self.toL2Bus)
self.toL2Bus.mem_side_ports = self.l2.cpu_side
def addPMUs(self, ints, events=[]):
@@ -184,7 +184,7 @@
self.l2.mem_side = bus.cpu_side_ports
except AttributeError:
for cpu in self.cpus:
- cpu.connectAllPorts(bus)
+ cpu.connectCachedPorts(bus)
class AtomicCluster(CpuCluster):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0f71f605ef73d9adc418414c891569bc475b2587
Gerrit-Change-Number: 52583
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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