Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/52488 )
Change subject: cpu: Remove an architecture check in
addPrivateSplitL1Caches.
......................................................................
cpu: Remove an architecture check in addPrivateSplitL1Caches.
If there are iwc and dwc parameters, then they need to be hooked up. If
not, then they don't. There's no need to check the ISA as well.
Change-Id: I98cb831ab6d3f829ccab80e128105245e434a35c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52488
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/BaseCPU.py
1 file changed, 30 insertions(+), 15 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 1fa4d9e..4814745 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -208,22 +208,21 @@
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
- if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
- if iwc and dwc:
- self.itb_walker_cache = iwc
- self.dtb_walker_cache = dwc
- self.mmu.connectWalkerPorts(
- iwc.cpu_side, dwc.cpu_side)
- self._cached_ports += ["itb_walker_cache.mem_side", \
- "dtb_walker_cache.mem_side"]
- else:
- self._cached_ports += ArchMMU.walkerPorts()
+ if iwc and dwc:
+ self.itb_walker_cache = iwc
+ self.dtb_walker_cache = dwc
+ self.mmu.connectWalkerPorts(
+ iwc.cpu_side, dwc.cpu_side)
+ self._cached_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
+ else:
+ self._cached_ports += ArchMMU.walkerPorts()
- # Checker doesn't need its own tlb caches because it does
- # functional accesses only
- if self.checker != NULL:
- self._cached_ports += [ "checker." + port
- for port in ArchMMU.walkerPorts() ]
+ # Checker doesn't need its own tlb caches because it does
+ # functional accesses only
+ if self.checker != NULL:
+ self._cached_ports += [ "checker." + port
+ for port in ArchMMU.walkerPorts() ]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
xbar=None):
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52488
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I98cb831ab6d3f829ccab80e128105245e434a35c
Gerrit-Change-Number: 52488
Gerrit-PatchSet: 7
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
