Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56592 )
Change subject: arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
......................................................................
arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap
The mcrMrc15TrapToHyp helper is already called within mcrMrc15Trap
This achieves the following:
1) Simplifies ISA code
2) Aligns McrDc to Mcr instruction
Change-Id: I9b6bc621ad89230ad9dcf0563d8985d5757b4ae1
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/insts/misc.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
4 files changed, 42 insertions(+), 45 deletions(-)
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 4bb02c9..8c46cb8 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018, 2021 Arm Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -362,14 +362,7 @@
Fault
McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
- if (hypTrap) {
- return std::make_shared<HypervisorTrap>(machInst, iss,
- EC_TRAPPED_CP15_MCR_MRC);
- } else {
- return NoFault;
- }
+ return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
}
std::string
@@ -388,11 +381,9 @@
Fault
McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
- if (hypTrap) {
- return std::make_shared<HypervisorTrap>(machInst, iss,
- EC_TRAPPED_CP15_MCR_MRC);
+ Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
+ if (fault != NoFault) {
+ return fault;
} else {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 7253f85..f61c320 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2013,2017-2020 ARM Limited
+// Copyright (c) 2010-2013,2017-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1115,7 +1115,7 @@
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, preFlatDest)).index();
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
+ Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
@@ -1123,14 +1123,13 @@
// if we're in non secure PL1 mode then we can trap regardless
// of whether the register is accessible, in other modes we
// trap if only if the register IS accessible.
- if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
+ if (undefined || (!can_write && !(fault != NoFault
&& !inUserMode(Cpsr) &&
!isSecure(xc->tcBase())))) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
}
- if (hypTrap) {
- return std::make_shared<HypervisorTrap>(machInst, imm,
-
EC_TRAPPED_CP15_MCR_MRC);
+ if (fault != NoFault) {
+ return fault;
}
'''
@@ -1209,10 +1208,8 @@
isbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
- if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB,
- xc->tcBase(), imm)) {
- return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP15_MCR_MRC);
+ if (imm != 0) {
+ return mcrMrc15Trap(MISCREG_CP15ISB, machInst, xc->tcBase(),
imm);
}
'''
isbIop = ArmInstObjParams("isb", "Isb", "ImmOp",
@@ -1225,10 +1222,8 @@
dsbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
- if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB,
- xc->tcBase(), imm)) {
- return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP15_MCR_MRC);
+ if (imm != 0) {
+ return mcrMrc15Trap(MISCREG_CP15DSB, machInst, xc->tcBase(),
imm);
}
'''
dsbIop = ArmInstObjParams("dsb", "Dsb", "ImmOp",
@@ -1242,10 +1237,8 @@
dmbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
- if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB,
- xc->tcBase(), imm)) {
- return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP15_MCR_MRC);
+ if (imm != 0) {
+ return mcrMrc15Trap(MISCREG_CP15DMB, machInst, xc->tcBase(),
imm);
}
'''
dmbIop = ArmInstObjParams("dmb", "Dmb", "ImmOp",
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 6852aed..6013566 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -508,17 +508,7 @@
return (addr + PageBytes - 1) & ~(PageBytes - 1);
}
-Fault
-mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
- ThreadContext *tc, uint32_t imm)
-{
- ExceptionClass ec = EC_TRAPPED_CP15_MCR_MRC;
- if (mcrMrc15TrapToHyp(misc_reg, tc, imm, &ec))
- return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
- return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm,
ec);
-}
-
-bool
+static bool
mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t
iss,
ExceptionClass *ec)
{
@@ -672,6 +662,15 @@
return trap_to_hyp;
}
+Fault
+mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
+ ThreadContext *tc, uint32_t imm)
+{
+ ExceptionClass ec = EC_TRAPPED_CP15_MCR_MRC;
+ if (mcrMrc15TrapToHyp(misc_reg, tc, imm, &ec))
+ return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
+ return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm,
ec);
+}
bool
mcrMrc14TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t
iss)
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 00b0acf..cff1b5c 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -275,8 +275,6 @@
Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
ThreadContext *tc, uint32_t imm);
-bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
- uint32_t iss, ExceptionClass *ec=nullptr);
bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
uint32_t iss);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56592
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9b6bc621ad89230ad9dcf0563d8985d5757b4ae1
Gerrit-Change-Number: 56592
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
