Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56606 )
Change subject: arch-arm: Implement TLBI Shareable as a DVM op
......................................................................
arch-arm: Implement TLBI Shareable as a DVM op
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: Ie0a374abce41997af600773cc270a47cdf2c1338
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa/insts/data64.isa
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 038963d..6cc177e 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -378,12 +378,24 @@
decoder_output += MiscRegRegOp64Constructor.subst(msrTlbiIop)
exec_output += BasicExecute.subst(msrTlbiIop)
+ dvmCode = '''
+ if (machInst.dvmEnabled) {
+ Request::Flags memAccessFlags =
+ Request::STRICT_ORDER | Request::TLBI;
+
+ fault = xc->initiateSpecialMemCmd(memAccessFlags);
+
+ PendingDvm = true;
+ }
+ '''
msrTlbiSIop = ArmInstObjParams("msr", "Tlbi64ShareableHub", "TlbiOp64",
- tlbiCode,
+ { "code" : tlbiCode, "dvm_code" :
dvmCode },
["IsSerializeAfter", "IsNonSpeculative"])
- header_output += MiscRegRegOp64Declare.subst(msrTlbiSIop)
- decoder_output += MiscRegRegOp64Constructor.subst(msrTlbiSIop)
+ header_output += MiscRegRegMemOp64Declare.subst(msrTlbiSIop)
+ decoder_output += DvmTlbiConstructor.subst(msrTlbiSIop)
exec_output += BasicExecute.subst(msrTlbiSIop)
+ exec_output += DvmInitiateAcc.subst(msrTlbiSIop)
+ exec_output += DvmCompleteAcc.subst(msrTlbiSIop)
buildDataXRegInst("msrNZCV", 1, '''
CPSR cpsr = XOp1;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie0a374abce41997af600773cc270a47cdf2c1338
Gerrit-Change-Number: 56606
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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