Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49110 )
Change subject: cpu: Implement (get|set)Reg(Flat|) for SimpleThread.
......................................................................
cpu: Implement (get|set)Reg(Flat|) for SimpleThread.
Change-Id: Iddda31746606865d746df98e9e6d5adfa7266745
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49110
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/simple_thread.hh
1 file changed, 320 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 4d17ff1..8035bd9 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -483,6 +483,313 @@
}
RegVal
+ getReg(const RegId &arch_reg) const override
+ {
+ const RegId reg = flattenRegId(arch_reg);
+
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+ const RegIndex arch_idx = arch_reg.index();
+
+ RegVal val;
+ switch (type) {
+ case IntRegClass:
+ val = intRegs.reg(idx);
+ DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
+ arch_idx, idx, val);
+ return val;
+ case FloatRegClass:
+ val = floatRegs.reg(idx);
+ DPRINTF(FloatRegs, "Reading float reg %d (%d) as %#x.\n",
+ arch_idx, idx, val);
+ return val;
+ case VecElemClass:
+ val = vecElemRegs.reg(idx);
+ DPRINTF(VecRegs, "Reading vector element reg %d (%d)
as %#x.\n",
+ arch_idx, idx, val);
+ return val;
+ case CCRegClass:
+ val = ccRegs.reg(idx);
+ DPRINTF(CCRegs, "Reading cc reg %d (%d) as %#x.\n",
+ arch_idx, idx, val);
+ return val;
+ default:
+ panic("Unsupported register class type %d.", type);
+ }
+ }
+
+ RegVal
+ getRegFlat(const RegId ®) const override
+ {
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+
+ RegVal val;
+ switch (type) {
+ case IntRegClass:
+ val = intRegs.reg(idx);
+ DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", idx, val);
+ return val;
+ case FloatRegClass:
+ val = floatRegs.reg(idx);
+ DPRINTF(FloatRegs, "Reading float reg %d as %#x.\n", idx, val);
+ return val;
+ case VecElemClass:
+ val = vecElemRegs.reg(idx);
+ DPRINTF(VecRegs, "Reading vector element reg %d as %#x.\n",
+ idx, val);
+ return val;
+ case CCRegClass:
+ val = ccRegs.reg(idx);
+ DPRINTF(CCRegs, "Reading cc reg %d as %#x.\n", idx, val);
+ return val;
+ default:
+ panic("Unsupported register class type %d.", type);
+ }
+ }
+
+ void
+ getReg(const RegId &arch_reg, void *val) const override
+ {
+ const RegId reg = flattenRegId(arch_reg);
+
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+ const RegIndex arch_idx = arch_reg.index();
+
+ switch (type) {
+ case IntRegClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ case FloatRegClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ case VecRegClass:
+ vecRegs.get(idx, val);
+ DPRINTF(VecRegs, "Reading vector register %d (%d) as %s.\n",
+ arch_idx, idx, *(TheISA::VecRegContainer *)val);
+ break;
+ case VecElemClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ case VecPredRegClass:
+ vecPredRegs.get(idx, val);
+ DPRINTF(VecPredRegs, "Reading predicate register %d (%d)
as %s.\n",
+ arch_idx, idx, *(TheISA::VecRegContainer *)val);
+ break;
+ case CCRegClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
+ void
+ getRegFlat(const RegId ®, void *val) const override
+ {
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+
+ switch (type) {
+ case IntRegClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ case FloatRegClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ case VecRegClass:
+ vecRegs.get(idx, val);
+ DPRINTF(VecRegs, "Reading vector register %d as %s.\n",
+ idx, *(TheISA::VecRegContainer *)val);
+ break;
+ case VecElemClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ case VecPredRegClass:
+ vecPredRegs.get(idx, val);
+ DPRINTF(VecPredRegs, "Reading predicate register %d as %s.\n",
+ idx, *(TheISA::VecRegContainer *)val);
+ break;
+ case CCRegClass:
+ *(RegVal *)val = getRegFlat(reg);
+ break;
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
+ void *
+ getWritableReg(const RegId &arch_reg) override
+ {
+ const RegId reg = flattenRegId(arch_reg);
+
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+
+ switch (type) {
+ case VecRegClass:
+ return vecRegs.ptr(idx);
+ case VecPredRegClass:
+ return vecPredRegs.ptr(idx);
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
+ void *
+ getWritableRegFlat(const RegId ®) override
+ {
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+
+ switch (type) {
+ case VecRegClass:
+ return vecRegs.ptr(idx);
+ case VecPredRegClass:
+ return vecPredRegs.ptr(idx);
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
+ void
+ setReg(const RegId &arch_reg, RegVal val) override
+ {
+ const RegId reg = flattenRegId(arch_reg);
+
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+ const RegIndex arch_idx = arch_reg.index();
+
+ switch (type) {
+ case IntRegClass:
+ DPRINTF(IntRegs, "Setting int register %d (%d) to %#x.\n",
+ arch_idx, idx, val);
+ intRegs.reg(idx) = val;
+ break;
+ case FloatRegClass:
+ DPRINTF(FloatRegs, "Setting float register %d (%d) to %#x.\n",
+ arch_idx, idx, val);
+ floatRegs.reg(idx) = val;
+ break;
+ case VecElemClass:
+ DPRINTF(VecRegs, "Setting vector element register %d (%d) to "
+ "%#x.\n", arch_idx, idx, val);
+ vecElemRegs.reg(idx) = val;
+ break;
+ case CCRegClass:
+ DPRINTF(CCRegs, "Setting cc register %d (%d) to %#x.\n",
+ arch_idx, idx, val);
+ ccRegs.reg(idx) = val;
+ break;
+ default:
+ panic("Unsupported register class type %d.", type);
+ }
+ }
+
+ void
+ setRegFlat(const RegId ®, RegVal val) override
+ {
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+
+ switch (type) {
+ case IntRegClass:
+ DPRINTF(IntRegs, "Setting int register %d to %#x.\n", idx,
val);
+ intRegs.reg(idx) = val;
+ break;
+ case FloatRegClass:
+ DPRINTF(FloatRegs, "Setting float register %d to %#x.\n",
+ idx, val);
+ floatRegs.reg(idx) = val;
+ break;
+ case VecElemClass:
+ DPRINTF(VecRegs, "Setting vector element register %d
to %#x.\n",
+ idx, val);
+ vecElemRegs.reg(idx) = val;
+ break;
+ case CCRegClass:
+ DPRINTF(CCRegs, "Setting cc register %d to %#x.\n", idx, val);
+ ccRegs.reg(idx) = val;
+ break;
+ default:
+ panic("Unsupported register class type %d.", type);
+ }
+ }
+
+ void
+ setReg(const RegId &arch_reg, const void *val) override
+ {
+ const RegId reg = flattenRegId(arch_reg);
+
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+ const RegIndex arch_idx = arch_reg.index();
+
+ switch (type) {
+ case IntRegClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ case FloatRegClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ case VecRegClass:
+ DPRINTF(VecRegs, "Setting vector register %d (%d) to %s.\n",
+ idx, arch_idx, *(TheISA::VecRegContainer *)val);
+ vecRegs.set(idx, val);
+ break;
+ case VecElemClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ case VecPredRegClass:
+ DPRINTF(VecPredRegs, "Setting predicate register %d (%d)
to %s.\n",
+ idx, arch_idx, *(TheISA::VecRegContainer *)val);
+ vecPredRegs.set(idx, val);
+ break;
+ case CCRegClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
+ void
+ setRegFlat(const RegId ®, const void *val) override
+ {
+ const RegClassType type = reg.classValue();
+ const RegIndex idx = reg.index();
+
+ switch (type) {
+ case IntRegClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ case FloatRegClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ case VecRegClass:
+ DPRINTF(VecRegs, "Setting vector register %d to %s.\n",
+ idx, *(TheISA::VecRegContainer *)val);
+ vecRegs.set(idx, val);
+ break;
+ case VecElemClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ case VecPredRegClass:
+ DPRINTF(VecPredRegs, "Setting predicate register %d to %s.\n",
+ idx, *(TheISA::VecRegContainer *)val);
+ vecPredRegs.set(idx, val);
+ break;
+ case CCRegClass:
+ setRegFlat(reg, *(RegVal *)val);
+ break;
+ default:
+ panic("Unrecognized register class type %d.", type);
+ }
+ }
+
+ RegVal
readIntRegFlat(RegIndex idx) const override
{
return intRegs.reg(idx);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iddda31746606865d746df98e9e6d5adfa7266745
Gerrit-Change-Number: 49110
Gerrit-PatchSet: 43
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Alex Richardson <alexrichard...@google.com>
Gerrit-MessageType: merged
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