Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56711 )

Change subject: arch-x86: Manage the CPL properly when using an int gate.
......................................................................

arch-x86: Manage the CPL properly when using an int gate.

When using an int/call gate the CPL should reflect the DPL of the code
segment, or the CPL if the code segment is conforming.

Change-Id: If1a96472ca60b4229d2f8c78ec19d0c55d9e0c25
---
M src/arch/x86/microcode/romutil.ucode
M src/arch/x86/ucasmlib/arch/x86/microops/regop.py
2 files changed, 26 insertions(+), 4 deletions(-)



diff --git a/src/arch/x86/microcode/romutil.ucode b/src/arch/x86/microcode/romutil.ucode
index f0699a6..c738f36 100644
--- a/src/arch/x86/microcode/romutil.ucode
+++ b/src/arch/x86/microcode/romutil.ucode
@@ -57,8 +57,9 @@
 {start_label}_globalDescriptor:
     ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
 {start_label}_processDescriptor:
-    chks t0, t10, t3, IntCSCheck, dataSize=8
+    chks t10, t10, t3, IntCSCheck, dataSize=8
     wrdl hs, t3, t10, dataSize=8
+    wrsel hs, t10, dataSize=2

     # Stick the target offset in t9.
     wrdh t9, t4, t2, dataSize=8
@@ -119,8 +120,7 @@
     # Set up the target code segment. Do this now so we have the right
     # permissions when setting up the stack frame.
     #
-    srli t5, t4, 16, dataSize=8
-    andi t5, t5, 0xFF, dataSize=8
+    rdsel t5, hs, dataSize=8
     wrdl cs, t3, t5, dataSize=8
     # Tuck away the old CS for use below
     limm t10, 0, dataSize=8
@@ -231,7 +231,7 @@
     ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
 {start_label}_processCS:
     andi t13, t10, 0xff, dataSize=8
-    chks t0, t13, t3, IntCSCheck, dataSize=8
+    chks t13, t13, t3, IntCSCheck, dataSize=8
     wrdl hs, t3, t13, dataSize=8

     #
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/regop.py b/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
index 0ff7755..bca98e4 100644
--- a/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
@@ -1296,6 +1296,16 @@
                     fault = std::make_shared<GeneralProtection>(selector);
                 }
             }
+
+            if (m5reg.cpl < desc.dpl) {
+                fault = std::make_shared<GeneralProtection>(selector);
+            }
+            if (desc.type.c) {
+                selector.rpl = m5reg.cpl;
+            } else {
+                selector.rpl = desc.dpl;
+            }
+
             break;
           case SegTRCheck:
             if (!selector.si || selector.ti) {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If1a96472ca60b4229d2f8c78ec19d0c55d9e0c25
Gerrit-Change-Number: 56711
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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