Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56710 )
Change subject: arch-x86: Add a dest register for the chks microop.
......................................................................
arch-x86: Add a dest register for the chks microop.
This destination will be the selector that should be used in case the
RPL needs to be updated based on the DPL of a code segment for instance.
In all existing microcode, this register is set to t0 so the result is
thrown away, and currently the chks microop doesn't actually return any
adjusted selector. That will change soon.
Change-Id: Iaffaf4d6398dc944872fdd16d006901deeec6053
---
M
src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
M src/arch/x86/microcode/general_purpose/control_transfer/jump.ucode
M src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
M src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
M
src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
M src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
M src/arch/x86/microcode/romutil.ucode
M src/arch/x86/microcode/system/segmentation.ucode
M src/arch/x86/ucasmlib/arch/x86/microops/regop.py
9 files changed, 59 insertions(+), 53 deletions(-)
diff --git
a/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
b/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
index 30c6639..b2018f4 100644
---
a/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
+++
b/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
@@ -135,7 +135,7 @@
globalCSDescriptor:
ld t8, tsg, [1, t0, t6], dataSize=8, addressSize=8, atCPL0=True
processCSDescriptor:
- chks t2, t6, dataSize=8
+ chks t0, t2, t6, NoCheck, dataSize=8
###
@@ -192,7 +192,7 @@
globalSSDescriptor:
ld t7, tsg, [1, t0, t7], dataSize=8, addressSize=8, atCPL0=True
processSSDescriptor:
- chks t9, t7, dataSize=8
+ chks t0, t9, t7, NoCheck, dataSize=8
# This actually updates state which is wrong. It should wait until we
know
# we're not going to fault. Unfortunately, that's hard to do.
diff --git
a/src/arch/x86/microcode/general_purpose/control_transfer/jump.ucode
b/src/arch/x86/microcode/general_purpose/control_transfer/jump.ucode
index c66cca9..ca0a0cf 100644
--- a/src/arch/x86/microcode/general_purpose/control_transfer/jump.ucode
+++ b/src/arch/x86/microcode/general_purpose/control_transfer/jump.ucode
@@ -141,7 +141,7 @@
farJmpProcessDescriptor:
rcri t0, t4, 13, flags=(ECF,), dataSize=2
br "farJmpSystemDescriptor", flags=(nCECF,)
- chks t2, t4, CSCheck, dataSize=8
+ chks t0, t2, t4, CSCheck, dataSize=8
wrdl cs, t4, t2, dataSize=4
wrsel cs, t2, dataSize=4
wrip t0, t1, dataSize=4
diff --git
a/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
b/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
index 60475ed..99b5aed 100644
--- a/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
+++ b/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
@@ -147,7 +147,7 @@
globalDescriptor:
ld t3, tsg, [1, t0, t3], dataSize=8, addressSize=8
processDescriptor:
- chks t2, t3, IretCheck, dataSize=8
+ chks t0, t2, t3, IretCheck, dataSize=8
# There should be validity checks on the RIP checks here, but I'll do
# that later.
wrdl cs, t3, t2
diff --git
a/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
b/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
index e4a61c4..5b4a14a 100644
--- a/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
+++ b/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
@@ -273,7 +273,7 @@
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
- chks regm, t3, dataSize=8
+ chks t0, regm, t3, NoCheck, dataSize=8
wrdl sr, t3, regm
wrsel sr, regm
};
@@ -291,7 +291,7 @@
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
- chks t1, t3, dataSize=8
+ chks t0, t1, t3, NoCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
};
@@ -310,7 +310,7 @@
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
- chks t1, t3, dataSize=8
+ chks t0, t1, t3, NoCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
};
@@ -327,7 +327,7 @@
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
- chks regm, t3, SSCheck, dataSize=8
+ chks t0, regm, t3, SSCheck, dataSize=8
wrdl sr, t3, regm
wrsel sr, regm
};
@@ -345,7 +345,7 @@
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
- chks t1, t3, SSCheck, dataSize=8
+ chks t0, t1, t3, SSCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
};
@@ -364,7 +364,7 @@
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
- chks t1, t3, SSCheck, dataSize=8
+ chks t0, t1, t3, SSCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
};
diff --git
a/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
b/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
index 93ad246..d45c79b 100644
---
a/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
+++
b/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
@@ -97,7 +97,7 @@
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
- chks t1, t3, dataSize=8
+ chks t0, t1, t3, NoCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
diff --git
a/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
b/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
index 2509c3b..79ed36c 100644
--- a/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
+++ b/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
@@ -63,7 +63,7 @@
# Install the descriptor.
processDescriptor:
- chks t2, t4, {"SSCheck, " if seg == "ss" else ""}dataSize=8
+ chks t0, t2, t4, {"SSCheck" if seg == "ss" else "NoCheck"}, dataSize=8
wrdl {seg}, t4, t2
wrsel {seg}, t2
diff --git a/src/arch/x86/microcode/romutil.ucode
b/src/arch/x86/microcode/romutil.ucode
index 7dc26ae..f0699a6 100644
--- a/src/arch/x86/microcode/romutil.ucode
+++ b/src/arch/x86/microcode/romutil.ucode
@@ -42,7 +42,7 @@
ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8, atCPL0=True
# Make sure the descriptor is a legal gate.
- chks t1, t4, {gate_check_type}
+ chks t0, t1, t4, {gate_check_type}
#
# Get the target CS descriptor using the selector in the gate
@@ -57,7 +57,7 @@
{start_label}_globalDescriptor:
ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
{start_label}_processDescriptor:
- chks t10, t3, IntCSCheck, dataSize=8
+ chks t0, t10, t3, IntCSCheck, dataSize=8
wrdl hs, t3, t10, dataSize=8
# Stick the target offset in t9.
@@ -204,7 +204,7 @@
ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8, atCPL0=True
# Make sure the descriptor is a legal gate.
- chks t1, t4, {gate_check_type}, dataSize=8
+ chks t0, t1, t4, {gate_check_type}, dataSize=8
# Stick the target offset in t9.
wrdh t9, t4, t0, dataSize=8
@@ -231,7 +231,7 @@
ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
{start_label}_processCS:
andi t13, t10, 0xff, dataSize=8
- chks t13, t3, IntCSCheck, dataSize=8
+ chks t0, t13, t3, IntCSCheck, dataSize=8
wrdl hs, t3, t13, dataSize=8
#
@@ -277,7 +277,7 @@
{start_label}_globalSS:
ld t12, tsg, [1, t0, t11], dataSize=8, addressSize=8, atCPL0=True
{start_label}_processSS:
- chks t8, t12, SSCheck, dataSize=8
+ chks t0, t8, t12, SSCheck, dataSize=8
wrdl hs, t12, t8, dataSize=8
# Find the size of stack addresses based on this new descriptor.
diff --git a/src/arch/x86/microcode/system/segmentation.ucode
b/src/arch/x86/microcode/system/segmentation.ucode
index c88a34f..c656af1 100644
--- a/src/arch/x86/microcode/system/segmentation.ucode
+++ b/src/arch/x86/microcode/system/segmentation.ucode
@@ -168,12 +168,12 @@
{
.args 'R'
.serialize_after
- chks reg, t0, TRCheck
+ chks t0, reg, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
- chks reg, t1, TSSCheck
+ chks t0, reg, t1, TSSCheck
wrdh t3, t1, t2
wrdl tr, t1, reg
wrbase tr, t3, dataSize=8
@@ -187,12 +187,12 @@
.args 'M'
.serialize_after
ld t5, seg, sib, disp, dataSize=2
- chks t5, t0, TRCheck
+ chks t0, t5, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
- chks t5, t1, TSSCheck
+ chks t0, t5, t1, TSSCheck
wrdh t3, t1, t2
wrdl tr, t1, t5
wrbase tr, t3, dataSize=8
@@ -207,12 +207,12 @@
.serialize_after
rdip t7
ld t5, seg, riprel, disp, dataSize=2
- chks t5, t0, TRCheck
+ chks t0, t5, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
- chks t5, t1, TSSCheck
+ chks t0, t5, t1, TSSCheck
wrdh t3, t1, t2
wrdl tr, t1, t5
wrbase tr, t3, dataSize=8
@@ -225,11 +225,11 @@
{
.args 'R'
.serialize_after
- chks reg, t0, TRCheck
+ chks t0, reg, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
- chks reg, t1, TSSCheck
+ chks t0, reg, t1, TSSCheck
wrdl tr, t1, reg
limm t5, (1 << 9)
or t1, t1, t5
@@ -241,11 +241,11 @@
.args 'M'
.serialize_after
ld t5, seg, sib, disp, dataSize=2
- chks t5, t0, TRCheck
+ chks t0, t5, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
- chks t5, t1, TSSCheck
+ chks t0, t5, t1, TSSCheck
wrdl tr, t1, t5
limm t5, (1 << 9)
or t1, t1, t5
@@ -262,14 +262,14 @@
{
.args 'R'
.serialize_after
- chks reg, t0, InGDTCheck
+ chks t0, reg, t0, InGDTCheck
andi t0, reg, 0xf8, flags=(EZF,)
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
ld t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
- chks reg, t1, LDTCheck
+ chks t0, reg, t1, LDTCheck
wrdh t3, t1, t2
wrdl tsl, t1, reg
wrbase tsl, t3, dataSize=8
@@ -282,14 +282,14 @@
.args 'M'
.serialize_after
ld t5, seg, sib, disp, dataSize=2
- chks t5, t0, InGDTCheck
+ chks t0, t5, t0, InGDTCheck
andi t0, t5, 0xf8, flags=(EZF,)
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
ld t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
- chks t5, t1, LDTCheck
+ chks t0, t5, t1, LDTCheck
wrdh t3, t1, t2
wrdl tsl, t1, t5
wrbase tsl, t3, dataSize=8
@@ -303,14 +303,14 @@
.serialize_after
rdip t7
ld t5, seg, riprel, disp, dataSize=2
- chks t5, t0, InGDTCheck
+ chks t0, t5, t0, InGDTCheck
andi t0, t5, 0xf8, flags=(EZF,)
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
ld t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
- chks t5, t1, LDTCheck
+ chks t0, t5, t1, LDTCheck
wrdh t3, t1, t2
wrdl tsl, t1, t5
wrbase tsl, t3, dataSize=8
@@ -322,13 +322,13 @@
{
.args 'R'
.serialize_after
- chks reg, t0, InGDTCheck
+ chks t0, reg, t0, InGDTCheck
andi t0, reg, 0xf8, flags=(EZF,)
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
ld t1, tsg, [8, t4, t0], dataSize=8
- chks reg, t1, LDTCheck
+ chks t0, reg, t1, LDTCheck
wrdl tsl, t1, reg
end:
fault "NoFault"
@@ -339,13 +339,13 @@
.args 'M'
.serialize_after
ld t5, seg, sib, disp, dataSize=2
- chks t5, t0, InGDTCheck
+ chks t0, t5, t0, InGDTCheck
andi t0, t5, 0xf8, flags=(EZF,)
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
srli t4, t5, 3, dataSize=2
ld t1, tsg, [8, t4, t0], dataSize=8
- chks t5, t1, LDTCheck
+ chks t0, t5, t1, LDTCheck
wrdl tsl, t1, t5
end:
fault "NoFault"
diff --git a/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
b/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
index b5efbcf..0ff7755 100644
--- a/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
+++ b/src/arch/x86/ucasmlib/arch/x86/microops/regop.py
@@ -1216,18 +1216,17 @@
'''
class Chks(RegOp):
- operand_types = (FoldedSrc1Op, FoldedSrc2Op, Imm8Op)
- def __init__(self, src1, src2, imm=0, flags=None,
- dataSize="env.dataSize"):
- super().__init__(src1, src2, imm, flags=flags, dataSize=dataSize)
+ operand_types = (FoldedDestOp, FoldedSrc1Op, FoldedSrc2Op)
+ def __init__(self, dest, src1, src2, check, dataSize="env.dataSize"):
+ super().__init__(dest, src1, src2, flags=None, dataSize=dataSize)
+ self.ext = check
code = '''
// The selector is in source 1 and can be at most 16 bits.
SegSelector selector = SrcReg1;
SegDescriptor desc = SrcReg2;
HandyM5Reg m5reg = M5Reg;
- switch (imm8)
- {
+ switch (ext) {
case SegNoCheck:
break;
case SegCSCheck:
@@ -1328,16 +1327,7 @@
fault = std::make_shared<GenericISA::M5PanicFault>(
"Undefined segment check type.\\n");
}
- '''
- flag_code = '''
- // Check for a NULL selector and set ZF,EZF appropriately.
- PredccFlagBits = PredccFlagBits & ~(ext & ZFBit);
- PredezfBit = PredezfBit & ~(ext & EZFBit);
-
- if (!selector.si && !selector.ti) {
- PredccFlagBits = PredccFlagBits | (ext & ZFBit);
- PredezfBit = PredezfBit | (ext & EZFBit);
- }
+ DestReg = selector;
'''
class Wrdh(BasicRegOp):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaffaf4d6398dc944872fdd16d006901deeec6053
Gerrit-Change-Number: 56710
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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