Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49700 )
(
50 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: cpu: Remove readVecPredReg from ThreadContext::compare.
......................................................................
cpu: Remove readVecPredReg from ThreadContext::compare.
Use the generic getReg method to avoid having to use the
TheISA::VecPredRegContainer type.
Change-Id: I8240dd85f2db2f8125d7944135c4361866fba057
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49700
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/thread_context.cc
1 file changed, 30 insertions(+), 6 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 181c583..aab475b 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -41,6 +41,8 @@
#include "cpu/thread_context.hh"
+#include <vector>
+
#include "arch/generic/vec_pred_reg.hh"
#include "base/logging.hh"
#include "base/trace.hh"
@@ -91,13 +93,19 @@
}
// Then loop through the predicate registers.
- for (int i = 0; i < regClasses.at(VecPredRegClass).numRegs(); ++i) {
+ const auto &vec_pred_class = regClasses.at(VecPredRegClass);
+ std::vector<uint8_t> pred1(vec_pred_class.regBytes());
+ std::vector<uint8_t> pred2(vec_pred_class.regBytes());
+ for (int i = 0; i < vec_pred_class.numRegs(); ++i) {
RegId rid(VecPredRegClass, i);
- const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
- const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
- if (t1 != t2)
- panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
- i, t1, t2);
+
+ one->getReg(rid, pred1.data());
+ two->getReg(rid, pred2.data());
+ if (pred1 != pred2) {
+ panic("Pred reg idx %d doesn't match, one: %s, two: %s",
+ i, vec_pred_class.valString(pred1.data()),
+ vec_pred_class.valString(pred2.data()));
+ }
}
for (int i = 0; i < regClasses.at(MiscRegClass).numRegs(); ++i) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8240dd85f2db2f8125d7944135c4361866fba057
Gerrit-Change-Number: 49700
Gerrit-PatchSet: 52
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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