Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57194 )
Change subject: arch-x86: De-macro-ize the legacy mode interrupt microcode.
......................................................................
arch-x86: De-macro-ize the legacy mode interrupt microcode.
This microcode was specialized in two ways, first to set how the initial
gate was validated, and then second to optionally push an error code
onto the target stack.
It has now been rearranged so that its entry points call into other
blocks of microcode for the common parts, and each handle the small
parts that differ in the appropriate way.
Change-Id: Id580379176f99b695b5775c549740feea19f04a0
---
M src/arch/x86/microcode/romutil.ucode
1 file changed, 94 insertions(+), 68 deletions(-)
diff --git a/src/arch/x86/microcode/romutil.ucode
b/src/arch/x86/microcode/romutil.ucode
index 6e58be4..b70cd5a 100644
--- a/src/arch/x86/microcode/romutil.ucode
+++ b/src/arch/x86/microcode/romutil.ucode
@@ -176,8 +176,64 @@
undef macro long_int;
-def macro legacy_int label_prefix=rnd_str(), with_ec=False
+def rom
{
+ ############################################
+ # Entry points for legacy mode interrupts. #
+ ############################################
+extern legacyModeInterrupt:
+ bsr "legacy_mode_int_get_gate"
+
+ # Make sure the descriptor is a legal gate.
+ chks t0, t0, t1, IntGateCheck, dataSize=8
+ bsr "legacy_mode_int_work"
+ br "legacy_mode_int_finalize"
+
+extern legacyModeSoftInterrupt:
+ bsr "legacy_mode_int_get_gate"
+
+ # Make sure the descriptor is a legal gate.
+ chks t0, t0, t1, SoftIntGateCheck, dataSize=8
+ bsr "legacy_mode_int_work"
+ br "legacy_mode_int_finalize"
+
+extern legacyModeInterruptWithError:
+ bsr "legacy_mode_int_get_gate"
+
+ # Make sure the descriptor is a legal gate.
+ chks t0, t0, t1, IntGateCheck, dataSize=8
+ bsr "legacy_mode_int_work"
+
+ # Push an appropriately sized error code onto the target stack.
+
+ br "legacy_mode_int_push_ec_dsz_is_4", flags=(CECF,)
+
+ subi t5, t5, 2, dataSize=ssz
+ st t15, hs, [1, t0, t5], 0, dataSize=2, addressSize=ssz
+ br "legacy_mode_int_finalize"
+
+legacy_mode_int_push_ec_dsz_is_4:
+ subi t5, t5, 4, dataSize=ssz
+ st t15, hs, [1, t0, t5], 0, dataSize=4, addressSize=ssz
+ br "legacy_mode_int_finalize"
+
+
+ ####################################################
+ # A small helper to read in the gate from the IDT. #
+ ####################################################
+legacy_mode_int_get_gate:
+ # Load the gate descriptor from the IDT
+ slli t1, t1, 3, dataSize=8
+ ld t1, idtr, [1, t0, t1], dataSize=8, addressSize=8, atCPL0=True
+
+ sret
+
+
+ ##########################################
+ # The majority of the work is done here. #
+ ##########################################
+legacy_mode_int_work:
+
# Starred values are already set on entry.
# *t1 = gate descriptor
# t2 = target offset
@@ -231,7 +287,7 @@
# permissions for the stack accesses further down.
m_copy_seg_info dest="cs", source="hs", temp_reg="t8"
- br "{label_prefix}_stackSwitch", flags=(nCEZF,)
+ br "legacy_mode_int_stack_switch", flags=(nCEZF,)
# Set up a temporary stack pointer.
mov t5, rsp, rsp, dataSize=8
@@ -241,46 +297,47 @@
m_copy_seg_info dest="hs", source="ss", temp_reg="t8"
- br "{label_prefix}_dszIs4", flags=(CECF,)
- br "{label_prefix}_dszIs2"
+ br "legacy_mode_int_dsz_is_4", flags=(CECF,)
+ br "legacy_mode_int_dsz_is_2"
-{label_prefix}_stackSwitch:
- br "{label_prefix}_switchDszIs4", flags=(CECF,)
+legacy_mode_int_stack_switch:
+ br "legacy_mode_int_switch_dsz_is_4", flags=(CECF,)
m_switch_legacy_stack new_ptr="t5", new_seg="hs", new_cpl="t4", \
temp_reg="t8", data_size=2
-{label_prefix}_dszIs2:
+legacy_mode_int_dsz_is_2:
st t6, hs, [1, t0, t5], -2, dataSize=2, addressSize=ssz
st t3, hs, [1, t0, t5], -4, dataSize=2, addressSize=ssz
st t7, hs, [1, t0, t5], -6, dataSize=2, addressSize=ssz
- subi t6, t6, {8 if with_ec else 6}, dataSize=ssz
- {"st t15, hs, [1, t0, t5], " if with_ec else "#"} \
- {"dataSize=2, addressSize=ssz" if with_ec else ""}
+ subi t6, t6, 6, dataSize=ssz
- br "{label_prefix}_updateESP", flags=(CEZF,)
- br "{label_prefix}_updateSS"
+ sret
-{label_prefix}_switchDszIs4:
+legacy_mode_int_switch_dsz_is_4:
m_switch_legacy_stack new_ptr="t5", new_seg="hs", new_cpl="t4", \
temp_reg="t8", data_size=4
-{label_prefix}_dszIs4:
+legacy_mode_int_dsz_is_4:
st t6, hs, [1, t0, t5], -4, dataSize=4, addressSize=ssz
st t3, hs, [1, t0, t5], -8, dataSize=4, addressSize=ssz
st t7, hs, [1, t0, t5], -12, dataSize=4, addressSize=ssz
- subi t5, t5, {16 if with_ec else 12}, dataSize=ssz
- {"st t15, ss, [1, t0, t5], " if with_ec else "#"} \
- {"dataSize=4, addressSize=ssz" if with_ec else ""}
+ subi t5, t5, 12, dataSize=ssz
- br "{label_prefix}_updateESP", flags=(CEZF,)
+ sret
-{label_prefix}_updateSS:
+
+ ####################################################
+ # Finish vectoring by setting architectural state. #
+ ####################################################
+legacy_mode_int_finalize:
+
+ br "legacy_mode_int_update_ESP", flags=(CEZF,)
m_copy_seg_info dest="ss", source="hs", temp_reg="t8"
-{label_prefix}_updateESP:
+legacy_mode_int_update_ESP:
mov rsp, rsp, t5, dataSize=4
wrip t0, t2, dataSize=8
@@ -311,54 +368,6 @@
def rom
{
- # These vectors the CPU into an interrupt handler in legacy mode.
- # On entry, t1 is set to the vector of the interrupt and t7 is the
current
- # ip. We need that because rdip returns the next ip. t15 is the error
code,
- # if any.
-
-legacy_mode_int_get_gate:
- # Load the gate descriptor from the IDT
- slli t1, t1, 3, dataSize=8
- ld t1, idtr, [1, t0, t1], dataSize=8, addressSize=8, atCPL0=True
-
- sret
-
-legacy_mode_int_finalize:
-
-extern legacyModeInterrupt:
- bsr "legacy_mode_int_get_gate"
-
- # Make sure the descriptor is a legal gate.
- chks t0, t0, t1, IntGateCheck, dataSize=8
- legacy_int
-
-extern legacyModeSoftInterrupt:
- bsr "legacy_mode_int_get_gate"
-
- # Make sure the descriptor is a legal gate.
- chks t0, t0, t1, SoftIntGateCheck, dataSize=8
- legacy_int
-
-extern legacyModeInterruptWithError:
- bsr "legacy_mode_int_get_gate"
-
- # Make sure the descriptor is a legal gate.
- chks t0, t0, t1, IntGateCheck, dataSize=8
- legacy_int with_ec=True
-};
-
-undef macro legacy_int;
-
-def rom
-{
- # This vectors the CPU into an interrupt handler in legacy mode.
- extern legacyModeInterrupt:
- panic "Legacy mode interrupts not implemented (in microcode)"
- eret
-};
-
-def rom
-{
extern initIntHalt:
rflags t1
limm t2, "~IFBit"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id580379176f99b695b5775c549740feea19f04a0
Gerrit-Change-Number: 57194
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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