Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57193 )
Change subject: arch-x86: Make register usage in legacy int ucode
systematic.
......................................................................
arch-x86: Make register usage in legacy int ucode systematic.
When a value persists and needs to be preserved, put it in the low
numbered registers. When it's a temporary, put it in the high (above 7)
numbered registers, except 15 which is still the error code, if any.
Also agressively reuse temporaries so it's more obvious when they're no
longer necessary to keep.
Change-Id: I40aae7d3dd2ad058b7752b55d6981d622ccd6da9
---
M src/arch/x86/microcode/romutil.ucode
1 file changed, 79 insertions(+), 50 deletions(-)
diff --git a/src/arch/x86/microcode/romutil.ucode
b/src/arch/x86/microcode/romutil.ucode
index ab5f77e..6e58be4 100644
--- a/src/arch/x86/microcode/romutil.ucode
+++ b/src/arch/x86/microcode/romutil.ucode
@@ -178,17 +178,27 @@
def macro legacy_int label_prefix=rnd_str(), with_ec=False
{
- # t1 = gate descriptor
- # t7 = return IP
- # t15 = error code (if any)
+ # Starred values are already set on entry.
+ # *t1 = gate descriptor
+ # t2 = target offset
+ # t3 = original CS
+ # t4 = new CPL
+ # t5 = new ESP
+ # t6 = rflags
+ # *t7 = return IP
+ # t8-t14 = temporaries
+ # *t15 = error code (if any)
- # Stick the target offset in t9.
- wrdh t9, t1, t0, dataSize=8
+ # Stick the target offset in t2.
+ wrdh t2, t1, t0, dataSize=8
+
+ # Save the original CS.
+ rdsel t3, cs, dataSize=8
# Check the gate type.
- srli t2, t1, 40, dataSize=8
- andi t2, t2, 0xf, dataSize=8
- xori t2, t2, 0x5, flags=(EZF,), dataSize=8
+ srli t8, t1, 40, dataSize=8
+ andi t8, t8, 0xf, dataSize=8
+ xori t8, t8, 0x5, flags=(EZF,), dataSize=8
panic "Protected mode interrupt through a task gate not implemented.",
\
flags=(CEZF,)
@@ -197,11 +207,12 @@
# Get the target CS descriptor using the selector in the gate
# descriptor.
#
- srli t10, t1, 16, dataSize=8
- m_read_descriptor desc="t3", selector="t10"
- andi t13, t10, 0xff, dataSize=8
- chks t13, t13, t3, IntCSCheck, dataSize=8
- wrdl hs, t3, t13, dataSize=8
+ srli t8, t1, 16, dataSize=8
+ m_read_descriptor desc="t9", selector="t8"
+ andi t8, t8, 0xff, dataSize=8
+ chks t8, t8, t9, IntCSCheck, dataSize=8
+ wrdl hs, t9, t8, dataSize=8
+ wrsel hs, t8, dataSize=8
#
# Figure out stack stuff.
@@ -210,25 +221,25 @@
# Determine the operand size. ECF will be 1 if 32 bit, and 0 if 16 bit.
srli t0, t1, 44, flags=(ECF,), dataSize=8
- rdsel t11, cs, dataSize=8
-
# Check if we're changing privelege level. At this point we can assume
# we're going to a DPL that's less than or equal to the CPL.
- m_get_seg_priv_level pl="t10", seg="cs"
- m_get_seg_priv_level pl="t5", seg="hs"
- sub t0, t5, t10, flags=(EZF,), dataSize=8
+ m_get_seg_priv_level pl="t8", seg="cs"
+ m_get_seg_priv_level pl="t4", seg="hs"
+ sub t0, t4, t8, flags=(EZF,), dataSize=8
# We shouldn't modify CS here, but we need to so we have the right
# permissions for the stack accesses further down.
- wrsel cs, t13, dataSize=8
- wrdl cs, t3, t13, dataSize=8
+ m_copy_seg_info dest="cs", source="hs", temp_reg="t8"
br "{label_prefix}_stackSwitch", flags=(nCEZF,)
# Set up a temporary stack pointer.
- mov t6, rsp, rsp, dataSize=8
+ mov t5, rsp, rsp, dataSize=8
- m_copy_seg_info dest="hs", source="ss", temp_reg="t10"
+ # Grab RFLAGS for use further down.
+ rflags t6, dataSize=8
+
+ m_copy_seg_info dest="hs", source="ss", temp_reg="t8"
br "{label_prefix}_dszIs4", flags=(CECF,)
br "{label_prefix}_dszIs2"
@@ -236,61 +247,64 @@
{label_prefix}_stackSwitch:
br "{label_prefix}_switchDszIs4", flags=(CECF,)
- m_switch_legacy_stack new_ptr="t6", new_seg="hs", new_cpl="t5", \
+ m_switch_legacy_stack new_ptr="t5", new_seg="hs", new_cpl="t4", \
temp_reg="t8", data_size=2
{label_prefix}_dszIs2:
- rflags t10, dataSize=8
- st t10, hs, [1, t0, t6], -2, dataSize=2, addressSize=ssz
- st t11, hs, [1, t0, t6], -4, dataSize=2, addressSize=ssz
- st t7, hs, [1, t0, t6], -6, dataSize=2, addressSize=ssz
+ st t6, hs, [1, t0, t5], -2, dataSize=2, addressSize=ssz
+ st t3, hs, [1, t0, t5], -4, dataSize=2, addressSize=ssz
+ st t7, hs, [1, t0, t5], -6, dataSize=2, addressSize=ssz
subi t6, t6, {8 if with_ec else 6}, dataSize=ssz
- {"st t15, hs, [1, t0, t6], " if with_ec else "#"} \
+ {"st t15, hs, [1, t0, t5], " if with_ec else "#"} \
{"dataSize=2, addressSize=ssz" if with_ec else ""}
br "{label_prefix}_updateESP", flags=(CEZF,)
br "{label_prefix}_updateSS"
{label_prefix}_switchDszIs4:
- m_switch_legacy_stack new_ptr="t6", new_seg="hs", new_cpl="t5", \
+ m_switch_legacy_stack new_ptr="t5", new_seg="hs", new_cpl="t4", \
temp_reg="t8", data_size=4
{label_prefix}_dszIs4:
- rflags t10, dataSize=8
- st t10, hs, [1, t0, t6], -4, dataSize=4, addressSize=ssz
- st t11, hs, [1, t0, t6], -8, dataSize=4, addressSize=ssz
- st t7, hs, [1, t0, t6], -12, dataSize=4, addressSize=ssz
- subi t6, t6, {16 if with_ec else 12}, dataSize=ssz
- {"st t15, ss, [1, t0, t6], " if with_ec else "#"} \
+ st t6, hs, [1, t0, t5], -4, dataSize=4, addressSize=ssz
+ st t3, hs, [1, t0, t5], -8, dataSize=4, addressSize=ssz
+ st t7, hs, [1, t0, t5], -12, dataSize=4, addressSize=ssz
+ subi t5, t5, {16 if with_ec else 12}, dataSize=ssz
+ {"st t15, ss, [1, t0, t5], " if with_ec else "#"} \
{"dataSize=4, addressSize=ssz" if with_ec else ""}
br "{label_prefix}_updateESP", flags=(CEZF,)
{label_prefix}_updateSS:
- m_copy_seg_info dest="ss", source="hs", temp_reg="t10"
+ m_copy_seg_info dest="ss", source="hs", temp_reg="t8"
{label_prefix}_updateESP:
- mov rsp, rsp, t6, dataSize=4
+ mov rsp, rsp, t5, dataSize=4
- wrip t0, t9, dataSize=8
-
- # Set IF to the lowest bit of the original gate type.
- # The type field of the original gate starts at bit 40.
+ wrip t0, t2, dataSize=8
# Set the TF, NT, RF, and VM bits. We'll flip them at the end.
- limm t6, "(TFBit | NTBit | RFBit | VMBit)", dataSize=8
- or t10, t10, t6, dataSize=8
- srli t5, t1, 40, dataSize=8
- srli t7, t10, 9, dataSize=8
- xor t5, t7, t5, dataSize=8
- andi t5, t5, 1, dataSize=8
- slli t5, t5, 9, dataSize=8
- or t6, t5, t6, dataSize=8
+ limm t8, "(TFBit | NTBit | RFBit | VMBit)", dataSize=8
+ or t6, t6, t8, dataSize=8
+
+ # Set IF to the lowest bit of the original gate type.
+ # Extract the LSB of the gate type.
+ srli t9, t1, 40, dataSize=8
+ # Extract the IF bit from the flags.
+ srli t10, t6, 9, dataSize=8
+ # Xor them, so that *that* xored with flags will leave the gate LSB in
IF.
+ xor t9, t10, t9, dataSize=8
+ # Make sure no other bits are set.
+ andi t9, t9, 1, dataSize=8
+ # Move the target bit back into position for IF.
+ slli t9, t9, 9, dataSize=8
+ # Or it into the inversion input.
+ or t8, t9, t8, dataSize=8
# Put the results into rflags
- wrflags t6, t10
+ wrflags t8, t6
eret
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I40aae7d3dd2ad058b7752b55d6981d622ccd6da9
Gerrit-Change-Number: 57193
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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