Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49713 )
(
52 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch,cpu: Replace num${Type}DestReg accessors with
numDestReg(type).
......................................................................
arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type).
Change-Id: I32be58cce831c8c7d5b9e3d3f49f428a06c722a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49713
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/isa_parser/operand_list.py
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/rename.cc
M src/cpu/static_inst.hh
4 files changed, 27 insertions(+), 48 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/isa_parser/operand_list.py
b/src/arch/isa_parser/operand_list.py
index 3da7386..c26fdf3 100755
--- a/src/arch/isa_parser/operand_list.py
+++ b/src/arch/isa_parser/operand_list.py
@@ -116,12 +116,6 @@
self.numSrcRegs = len(srcs)
self.numDestRegs = len(dests)
- self.numFPDestRegs = sum(r.isFloatReg() for r in dests)
- self.numIntDestRegs = sum(r.isIntReg() for r in dests)
- self.numVecDestRegs = sum(r.isVecReg() for r in dests)
- self.numVecPredDestRegs = sum(r.isVecPredReg() for r in dests)
- self.numCCDestRegs = sum(r.isCCReg() for r in dests)
- self.numMiscDestRegs = sum(r.isControlReg() for r in dests)
if len(mem) > 1:
error("Code block has more than one memory operand")
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 28b9086..c083d50 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -680,21 +680,10 @@
/** Returns the number of destination registers. */
size_t numDestRegs() const { return numDests(); }
- // the following are used to track physical register usage
- // for machines with separate int & FP reg files
- int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
- int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
- int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
- int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
- int8_t
- numVecElemDestRegs() const
+ size_t
+ numDestRegs(RegClassType type) const
{
- return staticInst->numVecElemDestRegs();
- }
- int8_t
- numVecPredDestRegs() const
- {
- return staticInst->numVecPredDestRegs();
+ return staticInst->numDestRegs(type);
}
/** Returns the logical register index of the i'th destination
register. */
diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc
index f198870..d6c4efe 100644
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -656,12 +656,12 @@
// Check here to make sure there are enough destination registers
// to rename to. Otherwise block.
- if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
- inst->numFPDestRegs(),
- inst->numVecDestRegs(),
- inst->numVecElemDestRegs(),
- inst->numVecPredDestRegs(),
- inst->numCCDestRegs())) {
+ if (!renameMap[tid]->canRename(inst->numDestRegs(IntRegClass),
+ inst->numDestRegs(FloatRegClass),
+ inst->numDestRegs(VecRegClass),
+ inst->numDestRegs(VecElemClass),
+ inst->numDestRegs(VecPredRegClass),
+ inst->numDestRegs(CCRegClass))) {
DPRINTF(Rename,
"Blocking due to "
" lack of free physical registers to rename to.\n");
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index e9bd63e..2275598 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -115,36 +115,19 @@
public:
/// @name Register information.
- /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(),
- /// numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs().
- /// The former two functions are used to track physical register usage
for
- /// machines with separate int & FP reg files, the next three are for
- /// machines with vector and predicate register files.
+ /// The sum of the different numDestRegs([type])-s equals
numDestRegs().
+ /// The per-type function is used to track physical register usage.
//@{
/// Number of source registers.
uint8_t numSrcRegs() const { return _numSrcRegs; }
/// Number of destination registers.
uint8_t numDestRegs() const { return _numDestRegs; }
- /// Number of floating-point destination regs.
- uint8_t numFPDestRegs() const { return
_numTypedDestRegs[FloatRegClass]; }
- /// Number of integer destination regs.
- uint8_t numIntDestRegs() const { return
_numTypedDestRegs[IntRegClass]; }
- /// Number of vector destination regs.
- uint8_t numVecDestRegs() const { return
_numTypedDestRegs[VecRegClass]; }
- /// Number of vector element destination regs.
+ /// Number of destination registers of a particular type.
uint8_t
- numVecElemDestRegs() const
+ numDestRegs(RegClassType type) const
{
- return _numTypedDestRegs[VecElemClass];
+ return _numTypedDestRegs[type];
}
- /// Number of predicate destination regs.
- uint8_t
- numVecPredDestRegs() const
- {
- return _numTypedDestRegs[VecPredRegClass];
- }
- /// Number of coprocesor destination regs.
- uint8_t numCCDestRegs() const { return _numTypedDestRegs[CCRegClass]; }
//@}
/// @name Flag accessors.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I32be58cce831c8c7d5b9e3d3f49f428a06c722a2
Gerrit-Change-Number: 49713
Gerrit-PatchSet: 56
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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