Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49720 )
(
53 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch: Get rid of the is${Type}Reg methods of the Operand
class.
......................................................................
arch: Get rid of the is${Type}Reg methods of the Operand class.
These are not used, and would prevent creating a truly generic register
operand class.
Change-Id: Ibffadc7a682b878aee8e632a0f85c06e91a60614
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49720
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/isa_parser/operand_types.py
1 file changed, 16 insertions(+), 39 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index 3a1e5a4..bf8184f 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -122,27 +122,6 @@
def isReg(self):
return 0
- def isFloatReg(self):
- return 0
-
- def isIntReg(self):
- return 0
-
- def isCCReg(self):
- return 0
-
- def isControlReg(self):
- return 0
-
- def isVecReg(self):
- return 0
-
- def isVecElem(self):
- return 0
-
- def isVecPredReg(self):
- return 0
-
def isPCState(self):
return 0
@@ -177,9 +156,6 @@
class IntRegOperand(RegOperand):
reg_class = 'IntRegClass'
- def isIntReg(self):
- return 1
-
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
@@ -246,9 +222,6 @@
class FloatRegOperand(RegOperand):
reg_class = 'FloatRegClass'
- def isFloatReg(self):
- return 1
-
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
@@ -310,9 +283,6 @@
super().__init__(parser, full_name, ext, is_src, is_dest)
self.elemExt = None
- def isVecReg(self):
- return 1
-
def makeDeclElem(self, elem_op):
(elem_name, elem_ext) = elem_op
(elem_spec, dflt_elem_ext) = self.elems[elem_name]
@@ -450,9 +420,6 @@
class VecElemOperand(RegOperand):
reg_class = 'VecElemClass'
- def isVecElem(self):
- return 1
-
def makeDecl(self):
if self.is_dest and not self.is_src:
return '\n\t%s %s;' % (self.ctype, self.base_name)
@@ -494,9 +461,6 @@
class VecPredRegOperand(RegOperand):
reg_class = 'VecPredRegClass'
- def isVecPredReg(self):
- return 1
-
def makeDecl(self):
return ''
@@ -571,9 +535,6 @@
class CCRegOperand(RegOperand):
reg_class = 'CCRegClass'
- def isCCReg(self):
- return 1
-
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49720
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibffadc7a682b878aee8e632a0f85c06e91a60614
Gerrit-Change-Number: 49720
Gerrit-PatchSet: 58
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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