[gem5-dev] [S] Change in gem5/gem5[develop]: cpu-o3: print VecPredReg not VecReg

[Sascha Bischoff (Gerrit)]

Sascha Bischoff has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/64342?usp=email )

Change subject: cpu-o3: print VecPredReg not VecReg
......................................................................

cpu-o3: print VecPredReg not VecReg

Fix a DPRINTF to print the VecPredReg instead of the VecReg.

Change-Id: Iaba255b6b9a98826ddcd67eb83b4169e1bf5056e
---
M src/cpu/o3/regfile.hh
1 file changed, 12 insertions(+), 1 deletion(-)



diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 3a87fff..13c9899 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -316,7 +316,7 @@
             break;
           case VecPredRegClass:
             DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
-                    idx, vectorRegFile.regClass.valString(val));
+                    idx, vecPredRegFile.regClass.valString(val));
             vecPredRegFile.set(idx, val);
             break;
           case MatRegClass:

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaba255b6b9a98826ddcd67eb83b4169e1bf5056e
Gerrit-Change-Number: 64342
Gerrit-PatchSet: 1
Gerrit-Owner: Sascha Bischoff <sascha.bisch...@arm.com>
Gerrit-MessageType: newchange
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