Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/64342?usp=email )
Change subject: cpu-o3: print VecPredReg not VecReg
......................................................................
cpu-o3: print VecPredReg not VecReg
Fix a DPRINTF to print the VecPredReg instead of the VecReg.
Change-Id: Iaba255b6b9a98826ddcd67eb83b4169e1bf5056e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64342
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/o3/regfile.hh
1 file changed, 17 insertions(+), 1 deletion(-)
Approvals:
kokoro: Regressions pass
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 0130c55..4fea589 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -299,7 +299,7 @@
break;
case VecPredRegClass:
DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
- idx, vectorRegFile.regClass.valString(val));
+ idx, vecPredRegFile.regClass.valString(val));
vecPredRegFile.set(idx, val);
break;
case CCRegClass:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaba255b6b9a98826ddcd67eb83b4169e1bf5056e
Gerrit-Change-Number: 64342
Gerrit-PatchSet: 4
Gerrit-Owner: Sascha Bischoff <sascha.bisch...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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