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FS#230 - x86 segmentation support User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - x86 segmentation support Task Type - Minor Enhancement Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 50% Details - Added needed support for segmentation to support x86. First, it needs to be determined how much segmentation support we really need. If the processor is in long mode which is activated by the operating system, processes can operate in one of two sub modes. In the 64 bit submode, segmentation is ignored except for the attributes of the code segment (which determine if you're in 64 bit mode, among a few other things) and the bases and limits of the fs and gs segments. In the compatibility submode, processes see the segmentation semantics of the legacy protected mode, ie all of the user level features. Second, we need to decide where the support will come from. It can either be rolled into the paging mechanism, or it can be applied by the instructions themselves. I don't think it makes a difference as far as behavior, but putting it in the paging mechanism seems like a more logical place. The instructions apply the segment base and the tlb handles all the other details. There is currently no mechanism in place to let the target software change the segmentation registers. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/230 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
