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FS#250 - Revamp register handling mechanism User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Revamp register handling mechanism Task Type - Minor Enhancement Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - Currently, registers are either floating point, integer, or "misc". This doesn't fit naturally in architectures like x86 which have multiple floating point register files, and any architecture which has microregisters could use a second integer register file. Also, some "misc" registers are more like integer registers and should be renamed. An idea would be to allow defining an arbitrary number and combination of "register file" interfaces. These interfaces would allow access to registers which were either integer, floating point, or control. The floating point registers would be basically the same as the integer, except that they would have floating point return values in the accessors. The control registers would actually perform control functions, unlike the msic regs which are a mixture. Each of these interfaces would map from a potentially aliased or sparse register space into a packed, unambiguous register space which would be handled by the cpu. The actual backing store would be implemented as part of the cpu and not as part of the ISA. The exec contexts of the cpu would allow an operation very similar to changing the register file context, but this would change parameters in the register file interfaces. That would allow a dynamic mapping from the architected register space to a logical one to implement concepts like register windows or pal shadow registers. It might also be a good idea for each of these interfaces to export a set of properties which would allow the cpu to handle them properly. For instance, all register files could specify that they have "control" registers and shouldn't be renamed rather than having a seperate "control" register file interface. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/250 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
