alright, i'll dig a little and see what's up. On Mon, Sep 8, 2008 at 10:27 AM, nathan binkert <[EMAIL PROTECTED]> wrote: >> how long has SMT regressions been broke? Is this a new thing? >> >> I havent looked at O3 SMT in awhile, but I would assume the O3 changes >> over the past year or so take my "fix" time way up! >> >> Is there a particular changeset or marker where we can say it broke >> "here"...? > > It hasn't been broken for all that long, and the break is just that an > assertion is failing now that never used to fail. The assertion > started firing when Steve changed the default latency for main memory > to something longer and more realistic. I think Ali sent an e-mail a > few weeks ago with the exact changeset number, but given that it's an > assertion that now fails because a simple latency changed, I don't > know that the changeset helps all that much. The problem is that the > rest of us don't know enough to understand the assertion. > > Nate > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev >
-- ---------- Korey L Sewell Graduate Student - PhD Candidate Computer Science & Engineering University of Michigan _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
