changeset 08f836f37f61 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=08f836f37f61
description:
X86: Use the right portion of a register for stores.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/arch/x86/isa/microops/ldstop.isa | 4 ++--
diffs (15 lines):
diff -r c3d88393a1f3 -r 08f836f37f61 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Wed Feb 25 10:19:06 2009 -0800
+++ b/src/arch/x86/isa/microops/ldstop.isa Wed Feb 25 10:19:14 2009 -0800
@@ -466,9 +466,9 @@
microopClasses[name] = StoreOp
- defineMicroStoreOp('St', 'Mem = Data;')
+ defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
- defineMicroStoreOp('Stupd', 'Mem = Data;',
+ defineMicroStoreOp('Stupd', 'Mem = pick(Data, 2, dataSize);',
'Base = merge(Base, EA - SegBase, addressSize);',
'Base = merge(Base, pkt->req->getVaddr() - SegBase,
addressSize);');
defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
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