changeset 5a9c976270d6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a9c976270d6
description:
X86: Implement a basic prefetch instruction.
diffstat:
4 files changed, 42 insertions(+), 14 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 -
src/arch/x86/isa/includes.isa | 1
src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py | 28
++++++++--
src/arch/x86/isa/microops/ldstop.isa | 23
+++++---
diffs (161 lines):
diff -r 08f836f37f61 -r 5a9c976270d6
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:19:14
2009 -0800
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:19:22
2009 -0800
@@ -281,7 +281,7 @@
0x2: Inst::UD2();
0x3: Inst::UD2();
0x4: Inst::UD2();
- 0x5: prefetch();
+ 0x5: Inst::PREFETCH(Mb);
0x6: FailUnimpl::femms();
0x7: FailUnimpl::threednow();
}
@@ -335,7 +335,7 @@
//group17();
0x0: decode MODRM_REG {
0x0: prefetch_nta();
- 0x1: prefetch_t0();
+ 0x1: Inst::PREFETCH_T0(Mb);
0x2: prefetch_t1();
0x3: prefetch_t2();
default: Inst::HINT_NOP();
diff -r 08f836f37f61 -r 5a9c976270d6 src/arch/x86/isa/includes.isa
--- a/src/arch/x86/isa/includes.isa Wed Feb 25 10:19:14 2009 -0800
+++ b/src/arch/x86/isa/includes.isa Wed Feb 25 10:19:22 2009 -0800
@@ -157,6 +157,7 @@
#include "sim/sim_exit.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "mem/request.hh"
#include "sim/pseudo_inst.hh"
using namespace X86ISA;
diff -r 08f836f37f61 -r 5a9c976270d6
src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
--- a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
Wed Feb 25 10:19:14 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
Wed Feb 25 10:19:22 2009 -0800
@@ -53,7 +53,31 @@
#
# Authors: Gabe Black
-microcode = ""
+microcode = '''
+def macroop PREFETCH_M
+{
+ ld t0, seg, sib, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_P
+{
+ rdip t7
+ ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_T0_M
+{
+ ld t0, seg, sib, disp, dataSize=1, prefetch=True
+};
+
+def macroop PREFETCH_T0_P
+{
+ rdip t7
+ ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+};
+
+'''
+
#let {{
# class LFENCE(Inst):
# "GenFault ${new UnimpInstFault}"
@@ -63,8 +87,6 @@
# "GenFault ${new UnimpInstFault}"
# class PREFETCHlevel(Inst):
# "GenFault ${new UnimpInstFault}"
-# class PREFETCH(Inst):
-# "GenFault ${new UnimpInstFault}"
# class PREFETCHW(Inst):
# "GenFault ${new UnimpInstFault}"
# class CLFLUSH(Inst):
diff -r 08f836f37f61 -r 5a9c976270d6 src/arch/x86/isa/microops/ldstop.isa
--- a/src/arch/x86/isa/microops/ldstop.isa Wed Feb 25 10:19:14 2009 -0800
+++ b/src/arch/x86/isa/microops/ldstop.isa Wed Feb 25 10:19:22 2009 -0800
@@ -155,9 +155,11 @@
fault = read(xc, EA, Mem, memFlags);
- if(fault == NoFault)
- {
+ if (fault == NoFault) {
%(code)s;
+ } else if (memFlags & Request::PF_EXCLUSIVE) {
+ // For prefetches, ignore any faults/exceptions.
+ return NoFault;
}
if(fault == NoFault)
{
@@ -361,7 +363,7 @@
let {{
class LdStOp(X86Microop):
def __init__(self, data, segment, addr, disp,
- dataSize, addressSize, baseFlags, atCPL0):
+ dataSize, addressSize, baseFlags, atCPL0, prefetch):
self.data = data
[self.scale, self.index, self.base] = addr
self.disp = disp
@@ -371,6 +373,8 @@
self.memFlags = baseFlags
if atCPL0:
self.memFlags += " | (CPL0FlagBit << FlagShift)"
+ if prefetch:
+ self.memFlags += " | Request::PF_EXCLUSIVE"
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock
@@ -420,9 +424,10 @@
def __init__(self, data, segment, addr, disp = 0,
dataSize="env.dataSize",
addressSize="env.addressSize",
- atCPL0=False):
+ atCPL0=False, prefetch=False):
super(LoadOp, self).__init__(data, segment, addr,
- disp, dataSize, addressSize, mem_flags, atCPL0)
+ disp, dataSize, addressSize, mem_flags,
+ atCPL0, prefetch)
self.className = Name
self.mnemonic = name
@@ -460,7 +465,7 @@
addressSize="env.addressSize",
atCPL0=False):
super(StoreOp, self).__init__(data, segment, addr,
- disp, dataSize, addressSize, mem_flags, atCPL0)
+ disp, dataSize, addressSize, mem_flags, atCPL0, False)
self.className = Name
self.mnemonic = name
@@ -484,7 +489,7 @@
def __init__(self, data, segment, addr, disp = 0,
dataSize="env.dataSize", addressSize="env.addressSize"):
super(LeaOp, self).__init__(data, segment,
- addr, disp, dataSize, addressSize, "0", False)
+ addr, disp, dataSize, addressSize, "0", False, False)
self.className = "Lea"
self.mnemonic = "lea"
@@ -503,7 +508,7 @@
dataSize="env.dataSize",
addressSize="env.addressSize"):
super(TiaOp, self).__init__("NUM_INTREGS", segment,
- addr, disp, dataSize, addressSize, "0", False)
+ addr, disp, dataSize, addressSize, "0", False, False)
self.className = "Tia"
self.mnemonic = "tia"
@@ -514,7 +519,7 @@
dataSize="env.dataSize",
addressSize="env.addressSize", atCPL0=False):
super(CdaOp, self).__init__("NUM_INTREGS", segment,
- addr, disp, dataSize, addressSize, "0", atCPL0)
+ addr, disp, dataSize, addressSize, "0", atCPL0, False)
self.className = "Cda"
self.mnemonic = "cda"
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