For the TLB changes,
can someone elaborate on what the 3 modes mean {Read, Write, Execute}?I ask because in the translateAtomic function it seems as if the only modes that matter are Write and Execute. Why does Read not matter? I might be missing something simple, but it seems as if there are only 2 necessary modes (Inst/Data) and for the data portion we read the alpha system register to figure out if it's a read/write access. Thus, the 3rd argument to that function looks unnecessary since it is always the value "Write". If it is unneccessary, then does that not mess up the stats in that function who play off the "write" variable instead of maybe more appropriately the "mode" variable? Again, I might just be overlooking something. Can someone give me some insight into what's going on here? On Thu, Apr 9, 2009 at 1:26 AM, Gabe Black <gbl...@eecs.umich.edu> wrote: > changeset 410194bb3049 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=410194bb3049 > description: > tlb: Don't separate the TLB classes into an instruction TLB and a > data TLB > > diffstat: > > 34 files changed, 310 insertions(+), 601 deletions(-) > src/arch/alpha/AlphaTLB.py | 14 - > src/arch/alpha/tlb.cc | 253 > +++++++++++++++------------------ > src/arch/alpha/tlb.hh | 68 +++----- > src/arch/mips/MipsTLB.py | 20 -- > src/arch/mips/tlb.cc | 97 ++---------- > src/arch/mips/tlb.hh | 32 ---- > src/arch/sparc/SparcTLB.py | 14 - > src/arch/sparc/tlb.cc | 96 ++++-------- > src/arch/sparc/tlb.hh | 59 +------ > src/arch/sparc/vtophys.cc | 4 > src/arch/x86/X86TLB.py | 14 - > src/arch/x86/pagetable_walker.cc | 2 > src/arch/x86/tlb.cc | 61 +------ > src/arch/x86/tlb.hh | 50 +----- > src/cpu/BaseCPU.py | 26 +-- > src/cpu/checker/cpu.hh | 7 > src/cpu/checker/thread_context.hh | 4 > src/cpu/inorder/cpu.hh | 4 > src/cpu/inorder/resources/tlb_unit.cc | 2 > src/cpu/inorder/thread_context.hh | 4 > src/cpu/o3/cpu.hh | 4 > src/cpu/o3/fetch_impl.hh | 3 > src/cpu/o3/thread_context.hh | 4 > src/cpu/ozone/cpu.hh | 11 - > src/cpu/ozone/front_end_impl.hh | 2 > src/cpu/ozone/simple_params.hh | 5 > src/cpu/simple/atomic.cc | 2 > src/cpu/simple/timing.cc | 2 > src/cpu/simple/timing.hh | 6 > src/cpu/simple_thread.cc | 4 > src/cpu/simple_thread.hh | 12 - > src/cpu/thread_context.hh | 11 - > src/sim/tlb.cc | 7 > src/sim/tlb.hh | 7 > > diffs (truncated from 1715 to 300 lines): > > diff -r 6df0633d883b -r 410194bb3049 src/arch/alpha/AlphaTLB.py > --- a/src/arch/alpha/AlphaTLB.py Wed Apr 08 22:21:25 2009 -0700 > +++ b/src/arch/alpha/AlphaTLB.py Wed Apr 08 22:21:27 2009 -0700 > @@ -33,15 +33,5 @@ > > class AlphaTLB(BaseTLB): > type = 'AlphaTLB' > - abstract = True > - size = Param.Int("TLB size") > - > -class AlphaDTB(AlphaTLB): > - type = 'AlphaDTB' > - cxx_class = 'AlphaISA::DTB' > - size = 64 > - > -class AlphaITB(AlphaTLB): > - type = 'AlphaITB' > - cxx_class = 'AlphaISA::ITB' > - size = 48 > + cxx_class = 'AlphaISA::TLB' > + size = Param.Int(64, "TLB size") > diff -r 6df0633d883b -r 410194bb3049 src/arch/alpha/tlb.cc > --- a/src/arch/alpha/tlb.cc Wed Apr 08 22:21:25 2009 -0700 > +++ b/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700 > @@ -72,6 +72,90 @@ > delete [] table; > } > > +void > +TLB::regStats() > +{ > + fetch_hits > + .name(name() + ".fetch_hits") > + .desc("ITB hits"); > + fetch_misses > + .name(name() + ".fetch_misses") > + .desc("ITB misses"); > + fetch_acv > + .name(name() + ".fetch_acv") > + .desc("ITB acv"); > + fetch_accesses > + .name(name() + ".fetch_accesses") > + .desc("ITB accesses"); > + > + fetch_accesses = fetch_hits + fetch_misses; > + > + read_hits > + .name(name() + ".read_hits") > + .desc("DTB read hits") > + ; > + > + read_misses > + .name(name() + ".read_misses") > + .desc("DTB read misses") > + ; > + > + read_acv > + .name(name() + ".read_acv") > + .desc("DTB read access violations") > + ; > + > + read_accesses > + .name(name() + ".read_accesses") > + .desc("DTB read accesses") > + ; > + > + write_hits > + .name(name() + ".write_hits") > + .desc("DTB write hits") > + ; > + > + write_misses > + .name(name() + ".write_misses") > + .desc("DTB write misses") > + ; > + > + write_acv > + .name(name() + ".write_acv") > + .desc("DTB write access violations") > + ; > + > + write_accesses > + .name(name() + ".write_accesses") > + .desc("DTB write accesses") > + ; > + > + data_hits > + .name(name() + ".data_hits") > + .desc("DTB hits") > + ; > + > + data_misses > + .name(name() + ".data_misses") > + .desc("DTB misses") > + ; > + > + data_acv > + .name(name() + ".data_acv") > + .desc("DTB access violations") > + ; > + > + data_accesses > + .name(name() + ".data_accesses") > + .desc("DTB accesses") > + ; > + > + data_hits = read_hits + write_hits; > + data_misses = read_misses + write_misses; > + data_acv = read_acv + write_acv; > + data_accesses = read_accesses + write_accesses; > +} > + > // look up an entry in the TLB > TlbEntry * > TLB::lookup(Addr vpn, uint8_t asn) > @@ -288,36 +372,8 @@ > } > } > > -/////////////////////////////////////////////////////////////////////// > -// > -// Alpha ITB > -// > -ITB::ITB(const Params *p) > - : TLB(p) > -{} > - > - > -void > -ITB::regStats() > -{ > - hits > - .name(name() + ".hits") > - .desc("ITB hits"); > - misses > - .name(name() + ".misses") > - .desc("ITB misses"); > - acv > - .name(name() + ".acv") > - .desc("ITB acv"); > - accesses > - .name(name() + ".accesses") > - .desc("ITB accesses"); > - > - accesses = hits + misses; > -} > - > Fault > -ITB::translateAtomic(RequestPtr req, ThreadContext *tc) > +TLB::translateInst(RequestPtr req, ThreadContext *tc) > { > //If this is a pal pc, then set PHYSICAL > if (FULL_SYSTEM && PcPAL(req->getPC())) > @@ -326,7 +382,7 @@ > if (PcPAL(req->getPC())) { > // strip off PAL PC marker (lsb is 1) > req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); > - hits++; > + fetch_hits++; > return NoFault; > } > > @@ -335,7 +391,7 @@ > } else { > // verify that this is a good virtual address > if (!validVirtualAddress(req->getVaddr())) { > - acv++; > + fetch_acv++; > return new ItbAcvFault(req->getVaddr()); > } > > @@ -352,7 +408,7 @@ > // only valid in kernel mode > if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != > mode_kernel) { > - acv++; > + fetch_acv++; > return new ItbAcvFault(req->getVaddr()); > } > > @@ -373,7 +429,7 @@ > asn); > > if (!entry) { > - misses++; > + fetch_misses++; > return new ItbPageFault(req->getVaddr()); > } > > @@ -385,11 +441,11 @@ > if (!(entry->xre & > (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { > // instruction access fault > - acv++; > + fetch_acv++; > return new ItbAcvFault(req->getVaddr()); > } > > - hits++; > + fetch_hits++; > } > } > > @@ -401,93 +457,8 @@ > > } > > -void > -ITB::translateTiming(RequestPtr req, ThreadContext *tc, > - Translation *translation) > -{ > - assert(translation); > - translation->finish(translateAtomic(req, tc), req, tc, false); > -} > - > -/////////////////////////////////////////////////////////////////////// > -// > -// Alpha DTB > -// > -DTB::DTB(const Params *p) > - : TLB(p) > -{} > - > -void > -DTB::regStats() > -{ > - read_hits > - .name(name() + ".read_hits") > - .desc("DTB read hits") > - ; > - > - read_misses > - .name(name() + ".read_misses") > - .desc("DTB read misses") > - ; > - > - read_acv > - .name(name() + ".read_acv") > - .desc("DTB read access violations") > - ; > - > - read_accesses > - .name(name() + ".read_accesses") > - .desc("DTB read accesses") > - ; > - > - write_hits > - .name(name() + ".write_hits") > - .desc("DTB write hits") > - ; > - > - write_misses > - .name(name() + ".write_misses") > - .desc("DTB write misses") > - ; > - > - write_acv > - .name(name() + ".write_acv") > - .desc("DTB write access violations") > - ; > - > - write_accesses > - .name(name() + ".write_accesses") > - .desc("DTB write accesses") > - ; > - > - hits > - .name(name() + ".hits") > - .desc("DTB hits") > - ; > - > - misses > - .name(name() + ".misses") > - .desc("DTB misses") > - ; > - > - acv > - .name(name() + ".acv") > - .desc("DTB access violations") > - ; > - > - accesses > - .name(name() + ".accesses") > - .desc("DTB accesses") > - ; > - > - hits = read_hits + write_hits; > - misses = read_misses + write_misses; > - acv = read_acv + write_acv; > - accesses = read_accesses + write_accesses; > -} > - > Fault > -DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) > +TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) > { > Addr pc = tc->readPC(); > > @@ -624,14 +595,6 @@ > return checkCacheability(req); > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > -- ---------- Korey L Sewell Graduate Student - PhD Candidate Computer Science & Engineering University of Michigan
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