# HG changeset patch
# User Korey Sewell <[email protected]>
# Date 1239342519 14400
# Node ID d95ac474241eb0c7ce1ad1f71d57c60da547f946
# Parent 98211627847247ccd203e243c38e579a2e443b2b
create hello world regression for inorder-model
diff -r 982116278472 -r d95ac474241e tests/SConscript
--- a/tests/SConscript Fri Apr 10 01:48:39 2009 -0400
+++ b/tests/SConscript Fri Apr 10 01:48:39 2009 -0400
@@ -264,7 +264,7 @@ if env['FULL_SYSTEM']:
else:
configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
- 'simple-atomic-mp', 'simple-timing-mp']
+ 'simple-atomic-mp', 'simple-timing-mp', 'inorder-timing']
cwd = os.getcwd()
os.chdir(str(Dir('.').srcdir))
diff -r 982116278472 -r d95ac474241e
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini Fri Apr
10 01:48:39 2009 -0400
@@ -0,0 +1,226 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=1
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=10
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=10
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=10000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=10
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side
system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff -r 982116278472 -r d95ac474241e
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr Fri Apr
10 01:48:39 2009 -0400
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff -r 982116278472 -r d95ac474241e
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout Fri Apr
10 01:48:39 2009 -0400
@@ -0,0 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Apr 10 2009 00:47:42
+M5 revision 4483859fdebf 6034 default qtip tip inorder-hello-regress
+M5 started Apr 10 2009 00:47:43
+M5 executing on zooks
+command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 31646000 because target called exit()
diff -r 982116278472 -r d95ac474241e
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt Fri Apr
10 01:48:39 2009 -0400
@@ -0,0 +1,267 @@
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 154228 #
Number of bytes of host memory used
+host_seconds 0.28 #
Real time elapsed on the host
+host_tick_rate 114935098 #
Simulator tick rate (ticks/s)
+sim_freq 1000000000000 #
Frequency of simulated ticks
+sim_seconds 0.000032 #
Number of seconds simulated
+sim_ticks 31646000 #
Number of ticks simulated
+system.cpu.AGEN-Unit.instReqsProcessed 2050 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.instReqsProcessed 6405
# Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.predictedNotTaken 909
# Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 142
# Number of Branches Predicted As Taken (True).
+system.cpu.D-TLB.instReqsProcessed 2050 #
Number of Instructions Requests that completed in this resource.
+system.cpu.D-TLB.instsBypassed 0 #
Number of Instructions Bypassed.
+system.cpu.Decode-Unit.instReqsProcessed 6405 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.instReqsProcessed 4354
# Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 607
# Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 124
# Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Fetch-Buffer-T0.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Buffer-T0.instsBypassed 0 #
Number of Instructions Bypassed.
+system.cpu.Fetch-Buffer-T1.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Buffer-T1.instsBypassed 0 #
Number of Instructions Bypassed.
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 13560
# Number of Instructions Requests that completed in this resource.
+system.cpu.Graduation-Unit.instReqsProcessed 6404
# Number of Instructions Requests that completed in this resource.
+system.cpu.I-TLB.instReqsProcessed 7155 #
Number of Instructions Requests that completed in this resource.
+system.cpu.I-TLB.instsBypassed 0 #
Number of Instructions Bypassed.
+system.cpu.Mult-Div-Unit.divInstReqsProcessed 0
# Number of Divide Requests Processed.
+system.cpu.Mult-Div-Unit.instReqsProcessed 2
# Number of Instructions Requests that completed in this resource.
+system.cpu.Mult-Div-Unit.multInstReqsProcessed 1
# Number of Multiply Requests Processed.
+system.cpu.RegFile-Manager.instReqsProcessed 12884
# Number of Instructions Requests that completed in this resource.
+system.cpu.committedInsts 6404 #
Number of Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 6404 #
Number of Instructions Simulated (Total)
+system.cpu.cpi 9.883354 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 9.883354 #
CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1185 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56352.631579
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53352.631579
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1090 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5353500 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.080169 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 95 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 5068500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 95 #
number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 865 #
number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56419.540230
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.540230
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 778 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4908500 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.100578 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 87 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4647500
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 87 #
number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11.202381 #
Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 #
number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 #
number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 #
number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0
# number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 #
number of cache copies performed
+system.cpu.dcache.demand_accesses 2050 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56384.615385 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53384.615385
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 1868 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10262000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.088780 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 182 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 9716000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.088780 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 182 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 #
number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2050 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56384.615385
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53384.615385
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1868 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 10262000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.088780 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 182 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 9716000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.088780 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 182 #
number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 0 #
number of replacements
+system.cpu.dcache.sampled_refs 168 #
Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 104.325446 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 1882 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 #
number of writebacks
+system.cpu.dcache_port.instReqsProcessed 2050 #
Number of Instructions Requests that completed in this resource.
+system.cpu.dtb.data_accesses 2060 #
DTB accesses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_hits 2050 #
DTB hits
+system.cpu.dtb.data_misses 10 #
DTB misses
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
+system.cpu.dtb.read_accesses 1192 #
DTB read accesses
+system.cpu.dtb.read_acv 0 #
DTB read access violations
+system.cpu.dtb.read_hits 1185 #
DTB read hits
+system.cpu.dtb.read_misses 7 #
DTB read misses
+system.cpu.dtb.write_accesses 868 #
DTB write accesses
+system.cpu.dtb.write_acv 0 #
DTB write access violations
+system.cpu.dtb.write_hits 865 #
DTB write hits
+system.cpu.dtb.write_misses 3 #
DTB write misses
+system.cpu.icache.ReadReq_accesses 7155 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55763.605442
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52949.122807
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 6861 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16394500 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.041090 #
miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 294 #
number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 9 #
number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 15090500
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.039832 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 285 #
number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
+system.cpu.icache.avg_refs 24.158451 #
Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 #
number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 #
number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 #
number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0
# number of cycles access was blocked
+system.cpu.icache.cache_copies 0 #
number of cache copies performed
+system.cpu.icache.demand_accesses 7155 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55763.605442 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52949.122807
# average overall mshr miss latency
+system.cpu.icache.demand_hits 6861 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16394500 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.041090 #
miss rate for demand accesses
+system.cpu.icache.demand_misses 294 #
number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 9 #
number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 15090500
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.039832 #
mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 285 #
number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 #
number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 7155 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55763.605442
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52949.122807
# average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 6861 #
number of overall hits
+system.cpu.icache.overall_miss_latency 16394500 #
number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.041090 #
miss rate for overall accesses
+system.cpu.icache.overall_misses 294 #
number of overall misses
+system.cpu.icache.overall_mshr_hits 9 #
number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 15090500
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.039832 #
mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 285 #
number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 0 #
number of replacements
+system.cpu.icache.sampled_refs 284 #
Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 131.383181 #
Cycle average of tags in use
+system.cpu.icache.total_refs 6861 #
Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 #
number of writebacks
+system.cpu.icache_port.instReqsProcessed 7153 #
Number of Instructions Requests that completed in this resource.
+system.cpu.ipc 0.101180 #
IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.101180 #
IPC: Total IPC of All Threads
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.fetch_accesses 7172 #
ITB accesses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_hits 7155 #
ITB hits
+system.cpu.itb.fetch_misses 17 #
ITB misses
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_hits 0 #
DTB write hits
+system.cpu.itb.write_misses 0 #
DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 73 #
number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52424.657534
# average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630
# average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 3827000 #
number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 #
miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 73 #
number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000
# number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1
# mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 73 #
number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 380 #
number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52118.733509
# average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029
# average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1 #
number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19753000 #
number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.997368 #
miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 379 #
number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 15139000
# number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 #
mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 379 #
number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 14 #
number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52357.142857
# average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000
# average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 733000
# number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 #
miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 14 #
number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000
# number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1
# mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 14 #
number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.002747 #
Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 #
number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 #
number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0
# number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0
# number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 #
number of cache copies performed
+system.cpu.l2cache.demand_accesses 453 #
number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52168.141593
# average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212
# average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1 #
number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 23580000 #
number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997792 #
miss rate for demand accesses
+system.cpu.l2cache.demand_misses 452 #
number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 18060000
# number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.997792 #
mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 452 #
number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 #
number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 #
number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 453 #
number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52168.141593
# average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212
# average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1 #
number of overall hits
+system.cpu.l2cache.overall_miss_latency 23580000 #
number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997792 #
miss rate for overall accesses
+system.cpu.l2cache.overall_misses 452 #
number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 #
number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 18060000
# number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.997792 #
mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 452 #
number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 0 #
number of replacements
+system.cpu.l2cache.sampled_refs 364 #
Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0
# number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 182.840902 #
Cycle average of tags in use
+system.cpu.l2cache.total_refs 1 #
Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 #
number of writebacks
+system.cpu.numCycles 63293 #
number of cpu cycles simulated
+system.cpu.smtCommittedInsts 0 #
Number of SMT Instructions Simulated (Per-Thread)
+system.cpu.smtCycles 0 #
Total number of cycles that the CPU was simultaneous multithreading.(SMT)
+system.cpu.smt_cpi <err: div-0> #
CPI: Total SMT-CPI
+system.cpu.smt_ipc <err: div-0> #
IPC: Total SMT-IPC
+system.cpu.threadCycles 63293 #
Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.workload.PROG:num_syscalls 17 #
Number of system calls
+
+---------- End Simulation Statistics ----------
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