# HG changeset patch
# User Korey Sewell <[email protected]>
# Date 1239342519 14400
# Node ID ca55bb800d298db29634293b637e2e6a5eb31b3d
# Parent 1ea36de4c34568f7a3561fb9b7ed7393b725692b
Merge code to handle unified TLB.
diff -r 1ea36de4c345 -r ca55bb800d29 src/arch/alpha/regfile.hh
--- a/src/arch/alpha/regfile.hh Fri Apr 10 01:48:39 2009 -0400
+++ b/src/arch/alpha/regfile.hh Fri Apr 10 01:48:39 2009 -0400
@@ -36,6 +36,7 @@
#include "arch/alpha/intregfile.hh"
#include "arch/alpha/miscregfile.hh"
#include "arch/alpha/types.hh"
+#include "arch/alpha/mt.hh"
#include "sim/faults.hh"
#include <string>
diff -r 1ea36de4c345 -r ca55bb800d29 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Fri Apr 10 01:48:39 2009 -0400
+++ b/src/cpu/inorder/cpu.cc Fri Apr 10 01:48:39 2009 -0400
@@ -1270,17 +1270,17 @@ InOrderCPU::write(DynInstPtr inst)
return mem_res->doDataAccess(inst);
}
-TheISA::ITB*
+TheISA::TLB*
InOrderCPU::getITBPtr()
{
TLBUnit *itb_res = dynamic_cast<TLBUnit*>(resPool->getResource(itbIdx));
- return dynamic_cast<TheISA::ITB*>(itb_res->tlb());
-}
-
-
-TheISA::DTB*
+ return itb_res->tlb();
+}
+
+
+TheISA::TLB*
InOrderCPU::getDTBPtr()
{
TLBUnit *dtb_res = dynamic_cast<TLBUnit*>(resPool->getResource(dtbIdx));
- return dynamic_cast<TheISA::DTB*>(dtb_res->tlb());
-}
+ return dtb_res->tlb();
+}
diff -r 1ea36de4c345 -r ca55bb800d29 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Fri Apr 10 01:48:39 2009 -0400
+++ b/src/cpu/inorder/cpu.hh Fri Apr 10 01:48:39 2009 -0400
@@ -266,8 +266,8 @@ class InOrderCPU : public BaseCPU
/** Communication structure that sits in between pipeline stages */
StageQueue *stageQueue[ThePipeline::NumStages-1];
- TheISA::ITB *getITBPtr();
- TheISA::DTB *getDTBPtr();
+ TheISA::TLB *getITBPtr();
+ TheISA::TLB *getDTBPtr();
public:
diff -r 1ea36de4c345 -r ca55bb800d29 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Fri Apr 10 01:48:39 2009 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Fri Apr 10 01:48:39 2009 -0400
@@ -419,11 +419,10 @@ class InOrderDynInst : public FastAlloc,
/** Print Resource Schedule */
+ /** @NOTE: DEBUG ONLY */
void printSched()
{
- using namespace ThePipeline;
-
- ResSchedule tempSched;
+ ThePipeline::ResSchedule tempSched;
std::cerr << "\tInst. Res. Schedule: ";
while (!resSched.empty()) {
std::cerr << '\t' << resSched.top()->stageNum << "-"
@@ -837,7 +836,7 @@ class InOrderDynInst : public FastAlloc,
IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
FloatReg readFloatRegOperand(const StaticInst *si, int idx,
int width = TheISA::SingleWidth);
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
int width = TheISA::SingleWidth);
MiscReg readMiscReg(int misc_reg);
MiscReg readMiscRegNoEffect(int misc_reg);
@@ -880,7 +879,7 @@ class InOrderDynInst : public FastAlloc,
void setIntRegOperand(const StaticInst *si, int idx, IntReg val);
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
int width = TheISA::SingleWidth);
- void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits
val,
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
TheISA::FloatRegBits val,
int width = TheISA::SingleWidth);
void setMiscReg(int misc_reg, const MiscReg &val);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
diff -r 1ea36de4c345 -r ca55bb800d29 src/cpu/inorder/pipeline_traits.cc
--- a/src/cpu/inorder/pipeline_traits.cc Fri Apr 10 01:48:39 2009 -0400
+++ b/src/cpu/inorder/pipeline_traits.cc Fri Apr 10 01:48:39 2009 -0400
@@ -101,7 +101,7 @@ bool createBackEndSchedule(DynInstPtr &i
} else if ( inst->isMemRef() ) {
if ( inst->isLoad() ) {
E->needs(AGEN, AGENUnit::GenerateAddr);
- E->needs(DTLB, TLBUnit::DataLookup);
+ E->needs(DTLB, TLBUnit::DataReadLookup);
E->needs(DCache, CacheUnit::InitiateReadData);
}
} else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
@@ -122,7 +122,7 @@ bool createBackEndSchedule(DynInstPtr &i
} else if ( inst->isStore() ) {
M->needs(RegManager, UseDefUnit::ReadSrcReg, 1);
M->needs(AGEN, AGENUnit::GenerateAddr);
- M->needs(DTLB, TLBUnit::DataLookup);
+ M->needs(DTLB, TLBUnit::DataWriteLookup);
M->needs(DCache, CacheUnit::InitiateWriteData);
}
diff -r 1ea36de4c345 -r ca55bb800d29 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Fri Apr 10 01:48:39 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Fri Apr 10 01:48:39 2009 -0400
@@ -451,10 +451,12 @@ CacheUnit::processCacheCompletion(Packet
// Get resource request info
- // @todo: SMT needs to figure out where to get thread # from.
- unsigned tid = 0;
unsigned stage_num = cache_req->getStageNum();
DynInstPtr inst = cache_req->inst;
+ unsigned tid;
+
+
+ tid = cache_req->inst->readTid();
if (!cache_req->isSquashed()) {
if (inst->resSched.top()->cmd == CompleteFetch) {
diff -r 1ea36de4c345 -r ca55bb800d29 src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc Fri Apr 10 01:48:39 2009 -0400
+++ b/src/cpu/inorder/resources/tlb_unit.cc Fri Apr 10 01:48:39 2009 -0400
@@ -118,7 +118,7 @@ TLBUnit::execute(int slot_idx)
{
tlb_req->fault =
_tlb->translateAtomic(tlb_req->memReq,
- cpu->thread[tid]->getTC(), false, true);
+ cpu->thread[tid]->getTC(),
TheISA::TLB::Execute);
if (tlb_req->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while
translating "
@@ -142,14 +142,19 @@ TLBUnit::execute(int slot_idx)
}
break;
- case DataLookup:
+ case DataReadLookup:
+ case DataWriteLookup:
{
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i]: Attempting to translate
%08p.\n",
tid, seq_num, tlb_req->memReq->getVaddr());
+
+ TheISA::TLB::Mode tlb_mode = (tlb_req->cmd == DataReadLookup) ?
+ TheISA::TLB::Read : TheISA::TLB::Write;
+
tlb_req->fault =
_tlb->translateAtomic(tlb_req->memReq,
- cpu->thread[tid]->getTC());
+ cpu->thread[tid]->getTC(), tlb_mode);
if (tlb_req->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while
translating "
diff -r 1ea36de4c345 -r ca55bb800d29 src/cpu/inorder/resources/tlb_unit.hh
--- a/src/cpu/inorder/resources/tlb_unit.hh Fri Apr 10 01:48:39 2009 -0400
+++ b/src/cpu/inorder/resources/tlb_unit.hh Fri Apr 10 01:48:39 2009 -0400
@@ -47,7 +47,8 @@ class TLBUnit : public InstBuffer {
enum TLBCommand {
FetchLookup,
- DataLookup
+ DataReadLookup,
+ DataWriteLookup
};
public:
@@ -103,7 +104,7 @@ class TLBUnitRequest : public ResourceRe
if (_cmd == TLBUnit::FetchLookup) {
aligned_addr = inst->getMemAddr();
- req_size = sizeof(MachInst);
+ req_size = sizeof(TheISA::MachInst);
flags = 0;
} else {
aligned_addr = inst->getMemAddr();;
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
