On Wed, Jul 01, 2009 at 10:09:55PM -0700, Gabe Black wrote:
> I'm going to commit my changes and presume that anything that breaks
> will end up being fixed with whatever else may be broken now. I don't
> think these changes are likely that broken so it should be ok.
I've been testing the code. Found some bugs in the decoder; fix
is attached.
I think there are also some bugs in the floating point support, but I've
not tried to fix these yet.
Here is a new testcase. It has been greatly expanded with new tests,
including tests for load and store with (probably...) all addressing
modes. Includes some benchmark code from the MRTC WCET benchmarks.
http://www.jwhitham.org.uk/c/vt/testcase.gz
--
Jack Whitham
[email protected]
diff -rU3 m5-vanilla/src/arch/arm/isa/decoder.isa
m5/src/arch/arm/isa/decoder.isa
--- m5-vanilla/src/arch/arm/isa/decoder.isa 2009-07-02 20:17:58.000000000
+0100
+++ m5/src/arch/arm/isa/decoder.isa 2009-07-02 21:48:15.000000000 +0100
@@ -84,7 +84,7 @@
0x9: decode PREPOST {
0: decode OPCODE {
0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
- 0x1: mla({{ Rn = resTemp = Rm * Rs; }}, none);
+ 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
0x2: WarnUnimpl::umall();
0x4: umull({{
resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
@@ -114,110 +114,142 @@
}
0xb: decode PUBWL {
format ArmStoreMemory {
- 0x0, 0x8: strh_({{ Mem.uh = Rd.uh;
- Rn = Rn + Rm; }},
- {{ EA = Rn; }});
- 0x4, 0xc: strh_il({{ Mem.uh = Rd.uh;
+ 0x0: strh_({{ Mem.uh = Rd;
+ Rn = Rn - Rm; }},
+ {{ EA = Rn; }});
+ 0x4: strh_i({{ Mem.uh = Rd;
+ Rn = Rn + hilo; }},
+ {{ EA = Rn; }});
+ 0x8: strh_u({{ Mem.uh = Rd;
+ Rn = Rn + Rm; }},
+ {{ EA = Rn; }});
+ 0xc: strh_ui({{ Mem.uh = Rd;
+ Rn = Rn + hilo; }},
+ {{ EA = Rn; }});
+ 0x10: strh_p({{ Mem.uh = Rd; }},
+ {{ EA = Rn - Rm; }});
+ 0x12: strh_pw({{ Mem.uh = Rd;
+ Rn = Rn - Rm; }},
+ {{ EA = Rn - Rm; }});
+ 0x14: strh_pi({{ Mem.uh = Rd; }},
+ {{ EA = Rn + hilo; }});
+ 0x16: strh_piw({{ Mem.uh = Rd;
+ Rn = Rn + hilo; }},
+ {{ EA = Rn + hilo; }});
+ 0x18: strh_pu({{ Mem.uh = Rd; }},
+ {{ EA = Rn + Rm; }});
+ 0x1a: strh_puw({{ Mem.uh = Rd;
+ Rn = Rn + Rm; }},
+ {{ EA = Rn + Rm; }});
+ 0x1c: strh_pui({{ Mem.uh = Rd; }},
+ {{ EA = Rn + hilo; }});
+ 0x1e: strh_puiw({{ Mem.uh = Rd;
Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x10, 0x18: strh_p({{ Mem.uh = Rd.uh; }},
- {{ EA = Rn + Rm; }});
- 0x12, 0x1a: strh_pw({{ Mem.uh = Rd.uh;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
- 0x14, 0x1c: strh_pil({{ Mem.uh = Rd.uh; }},
- {{ EA = Rn + hilo; }});
- 0x16, 0x1e: strh_piwl({{ Mem.uh = Rd.uh;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
+ {{ EA = Rn + hilo; }});
}
format ArmLoadMemory {
- 0x1, 0x9: ldrh_l({{ Rd.uh = Mem.uh;
+ 0x1: ldrh_l({{ Rd = Mem.uh;
+ Rn = Rn - Rm; }},
+ {{ EA = Rn; }});
+ 0x5: ldrh_il({{ Rd = Mem.uh;
+ Rn = Rn + hilo; }},
+ {{ EA = Rn; }});
+ 0x9: ldrh_ul({{ Rd = Mem.uh;
+ Rn = Rn + Rm; }},
+ {{ EA = Rn; }});
+ 0xd: ldrh_uil({{ Rd = Mem.uh;
+ Rn = Rn + hilo; }},
+ {{ EA = Rn; }});
+ 0x11: ldrh_pl({{ Rd = Mem.uh; }},
+ {{ EA = Rn - Rm; }});
+ 0x13: ldrh_pwl({{ Rd = Mem.uh;
+ Rn = Rn - Rm; }},
+ {{ EA = Rn - Rm; }});
+ 0x15: ldrh_pil({{ Rd = Mem.uh; }},
+ {{ EA = Rn + hilo; }});
+ 0x17: ldrh_piwl({{ Rd = Mem.uh;
+ Rn = Rn + hilo; }},
+ {{ EA = Rn + hilo; }});
+ 0x19: ldrh_pul({{ Rd = Mem.uh; }},
+ {{ EA = Rn + Rm; }});
+ 0x1b: ldrh_puwl({{ Rd = Mem.uh;
Rn = Rn + Rm; }},
- {{ EA = Rn; }});
- 0x5, 0xd: ldrh_il({{ Rd.uh = Mem.uh;
+ {{ EA = Rn + Rm; }});
+ 0x1d: ldrh_puil({{ Rd = Mem.uh; }},
+ {{ EA = Rn + hilo; }});
+ 0x1f: ldrh_puiwl({{ Rd = Mem.uh;
Rn = Rn + hilo; }},
- {{ EA = Rn; }});
- 0x11, 0x19: ldrh_pl({{ Rd.uh = Mem.uh; }},
- {{ EA = Rn + Rm; }});
- 0x13, 0x1b: ldrh_pwl({{ Rd.uh = Mem.uh;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
- 0x15, 0x1d: ldrh_pil({{ Rd.uh = Mem.uh; }},
- {{ EA = Rn + hilo; }});
- 0x17, 0x1f: ldrh_piwl({{ Rd.uh = Mem.uh;
- Rn = Rn + hilo; }},
- {{ EA = Rn + hilo; }});
+ {{ EA = Rn + hilo; }});
}
}
format ArmLoadMemory {
0xd: decode PUBWL {
0x1: ldrsb_l({{ Rd = Mem.sb;
- Rn = Rn + Rm; }},
+ Rn = Rn - Rm; }},
{{ EA = Rn; }});
0x5: ldrsb_il({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x9: ldrsb_ul({{ Rd = Mem.sb;
- Rn = Rn - Rm; }},
+ Rn = Rn + Rm; }},
{{ EA = Rn; }});
0xd: ldrsb_uil({{ Rd = Mem.sb;
- Rn = Rn - hilo; }},
- {{ EA = Rn; }});
+ Rn = Rn + hilo; }},
+ {{ EA = Rn; }});
0x11: ldrsb_pl({{ Rd = Mem.sb; }},
- {{ EA = Rn + Rm; }});
+ {{ EA = Rn - Rm; }});
0x13: ldrsb_pwl({{ Rd = Mem.sb;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
+ Rn = Rn - Rm; }},
+ {{ EA = Rn - Rm; }});
0x15: ldrsb_pil({{ Rd = Mem.sb; }},
{{ EA = Rn + hilo; }});
0x17: ldrsb_piwl({{ Rd = Mem.sb;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
0x19: ldrsb_pul({{ Rd = Mem.sb; }},
- {{ EA = Rn - Rm; }});
+ {{ EA = Rn + Rm; }});
0x1b: ldrsb_puwl({{ Rd = Mem.sb;
- Rn = Rn - Rm; }},
- {{ EA = Rn - Rm; }});
+ Rn = Rn + Rm; }},
+ {{ EA = Rn + Rm; }});
0x1d: ldrsb_puil({{ Rd = Mem.sb; }},
- {{ EA = Rn - hilo; }});
+ {{ EA = Rn + hilo; }});
0x1f: ldrsb_puiwl({{ Rd = Mem.sb;
- Rn = Rn - hilo; }},
- {{ EA = Rn - hilo; }});
+ Rn = Rn + hilo; }},
+ {{ EA = Rn + hilo; }});
}
0xf: decode PUBWL {
0x1: ldrsh_l({{ Rd = Mem.sh;
- Rn = Rn + Rm; }},
+ Rn = Rn - Rm; }},
{{ EA = Rn; }});
0x5: ldrsh_il({{ Rd = Mem.sh;
Rn = Rn + hilo; }},
{{ EA = Rn; }});
0x9: ldrsh_ul({{ Rd = Mem.sh;
- Rn = Rn - Rm; }},
+ Rn = Rn + Rm; }},
{{ EA = Rn; }});
0xd: ldrsh_uil({{ Rd = Mem.sh;
- Rn = Rn - hilo; }},
- {{ EA = Rn; }});
+ Rn = Rn + hilo; }},
+ {{ EA = Rn; }});
0x11: ldrsh_pl({{ Rd = Mem.sh; }},
- {{ EA = Rn + Rm; }});
+ {{ EA = Rn - Rm; }});
0x13: ldrsh_pwl({{ Rd = Mem.sh;
- Rn = Rn + Rm; }},
- {{ EA = Rn + Rm; }});
+ Rn = Rn - Rm; }},
+ {{ EA = Rn - Rm; }});
0x15: ldrsh_pil({{ Rd = Mem.sh; }},
{{ EA = Rn + hilo; }});
0x17: ldrsh_piwl({{ Rd = Mem.sh;
Rn = Rn + hilo; }},
{{ EA = Rn + hilo; }});
0x19: ldrsh_pul({{ Rd = Mem.sh; }},
- {{ EA = Rn - Rm; }});
+ {{ EA = Rn + Rm; }});
0x1b: ldrsh_puwl({{ Rd = Mem.sh;
- Rn = Rn - Rm; }},
- {{ EA = Rn - Rm; }});
+ Rn = Rn + Rm; }},
+ {{ EA = Rn + Rm; }});
0x1d: ldrsh_puil({{ Rd = Mem.sh; }},
- {{ EA = Rn - hilo; }});
+ {{ EA = Rn + hilo; }});
0x1f: ldrsh_puiwl({{ Rd = Mem.sh;
- Rn = Rn - hilo; }},
- {{ EA = Rn - hilo; }});
+ Rn = Rn + hilo; }},
+ {{ EA = Rn + hilo; }});
}
}
}
@@ -355,47 +387,91 @@
}
0x3: decode OPCODE_4 {
0: decode PUBWL {
- 0x00,0x08: ArmStoreMemory::strr_({{
+ 0x00: ArmStoreMemory::strr_({{
+ Mem = Rd;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn; }});
+ 0x08: ArmStoreMemory::strr_u({{
Mem = Rd;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn; }});
- 0x01,0x09: ArmLoadMemory::ldrr_l({{
+ 0x01: ArmLoadMemory::ldrr_l({{
+ Rd = Mem;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn; }});
+ 0x09: ArmLoadMemory::ldrr_lu({{
Rd = Mem;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn; }});
- 0x04,0x0c: ArmStoreMemory::strr_b({{
+ 0x04: ArmStoreMemory::strr_b({{
+ Mem.ub = Rd.ub;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn; }});
+ 0x0c: ArmStoreMemory::strr_bu({{
Mem.ub = Rd.ub;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn; }});
- 0x05,0x0d: ArmLoadMemory::ldrr_bl({{
+ 0x05: ArmLoadMemory::ldrr_bl({{
+ Rd.ub = Mem.ub;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn; }});
+ 0x0d: ArmLoadMemory::ldrr_bul({{
Rd.ub = Mem.ub;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn; }});
- 0x10,0x18: ArmStoreMemory::strr_p({{
+ 0x10: ArmStoreMemory::strr_p({{
+ Mem = Rd; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x18: ArmStoreMemory::strr_pu({{
Mem = Rd; }},
{{ EA = Rn + Rm_Imm; }});
- 0x11,0x19: ArmLoadMemory::ldrr_pl({{
+ 0x11: ArmLoadMemory::ldrr_pl({{
+ Rd = Mem; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x19: ArmLoadMemory::ldrr_pul({{
Rd = Mem; }},
{{ EA = Rn + Rm_Imm; }});
- 0x12,0x1a: ArmStoreMemory::strr_pw({{
+ 0x12: ArmStoreMemory::strr_pw({{
+ Mem = Rd;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x1a: ArmStoreMemory::strr_puw({{
Mem = Rd;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn + Rm_Imm; }});
- 0x13,0x1b: ArmLoadMemory::ldrr_pwl({{
+ 0x13: ArmLoadMemory::ldrr_pwl({{
+ Rd = Mem;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x1b: ArmLoadMemory::ldrr_puwl({{
Rd = Mem;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn + Rm_Imm; }});
- 0x14,0x1c: ArmStoreMemory::strr_pb({{
+ 0x14: ArmStoreMemory::strr_pb({{
+ Mem.ub = Rd.ub; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x1c: ArmStoreMemory::strr_pbu({{
Mem.ub = Rd.ub; }},
{{ EA = Rn + Rm_Imm; }});
- 0x15,0x1d: ArmLoadMemory::ldrr_pbl({{
+ 0x15: ArmLoadMemory::ldrr_pbl({{
+ Rd.ub = Mem.ub; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x1d: ArmLoadMemory::ldrr_pbul({{
Rd.ub = Mem.ub; }},
{{ EA = Rn + Rm_Imm; }});
- 0x16,0x1e: ArmStoreMemory::strr_pbw({{
+ 0x16: ArmStoreMemory::strr_pbw({{
+ Mem.ub = Rd.ub;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x1e: ArmStoreMemory::strr_pbuw({{
Mem.ub = Rd.ub;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn + Rm_Imm; }});
- 0x17,0x1f: ArmLoadMemory::ldrr_pbwl({{
+ 0x17: ArmLoadMemory::ldrr_pbwl({{
+ Rd.ub = Mem.ub;
+ Rn = Rn - Rm_Imm; }},
+ {{ EA = Rn - Rm_Imm; }});
+ 0x1f: ArmLoadMemory::ldrr_pbuwl({{
Rd.ub = Mem.ub;
Rn = Rn + Rm_Imm; }},
{{ EA = Rn + Rm_Imm; }});
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