> I haven't looked at your patch in great detail, but I suspect that there > might be a way to get that to work without new mechanisms. The devil is > in the details so we'll see what can be done. I do have a number of > changes that affect isa_parser.py and/or ARM's isa description. If you > can give me some sort of test to run, I can try to make sure that even > if things are done substantially differently your support will work as > well as it does now.
Ok. The exact mechanism doesn't matter to me as long as I can run O3 and ARM together. The changes in my op_copy_patch (last email) don't affect the functionality of the simple CPU. Unfortunately, the only way to test them is to use them with O3. And O3 + ARM support is very experimental, not in the main repository, and not fully working. However - I think I am ready to send you my work now: http://www.jwhitham.org.uk/c/vt/m5-qemu-test.tar.gz This test package can be used to verify both the simple CPU model and O3. A test program is run simultaneously in QEMU and M5, and the register state is compared whenever each instruction commits. This is how I found the bugs in the ISA definition. QEMU has to be modified to do this; source modifications and x86_64 binary are included. To use this package you have to patch M5 to add a new type of trace output called "ftr", which is a binary format. I started using ftr because of (1) the slow speed of parsing the human-readable trace format, and (2) the problem that the human-readable trace does not include all register information. The patch for ftr is called "add-ftr.patch" and it's in the package. I don't suggest that this should be added to M5 as a feature, it's only there to support my test. You can use the "patch" program to easily add and remove (-R) it. After compiling m5/build/ARM_SE/m5.debug with at least the "add-ftr.patch", you can run "./regression". This tests M5 in the simple CPU mode. This test will succeed whether you are using the current development version, or the development version and my patches. If you run "./regression --detailed --caches", you are testing M5 in O3 mode. This will fail unless you are using the development version and my "add-arm-o3.patch". Even if you are using my patch, it will still eventually fail (after around 30 million instructions committed) - there are still some bugs to fix! The first test "tc/testcase" is fast and should complete in a minute or two. The second test can run for hours, use control-C to save time :). Example usage: tar xvzf m5-qemu-test.tar.gz cd m5-qemu-test/m5 # current development snapshot patch -p1 <../add-ftr.patch scons build/ARM_SE/m5.debug cd .. ./regression # test of current development version cd m5 patch -p1 <../add-arm-o3.patch rm -rf build # build_opts directory changed.. scons build/ARM_SE/m5.debug cd .. ./regression --detailed --caches # test of my O3 + ARM changes. I hope this will be helpful for you. I have only tested this code on x86_64 Linux and so I don't know how portable it is. It is certainly not really packaged properly for widespread distribution. I have included modified source for QEMU and my "regression" program. Please email me if you have problems or questions about this test or the patch, etc. Thanks, Jack -- Jack Whitham [email protected] _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
