OK, I think I've fixed this.
The key is the line:
code = "int16_t simm8 = (int16_t)((int8_t)imm8);" + code
I had to change your patch to have the extra "int8_t" cast, or else
it wasn't sign extending the result.
Below is the updated patch, which works for my test.
Note, scons doesn't seem to see changes to regop.isa, at least on my
machine. I had to manually remove m5.opt to get it to rebuild.
Vince
diff -r cb4c4b793106 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Tue Sep 15 17:04:59 2009 -0400
+++ b/src/arch/x86/isa/microops/regop.isa Wed Sep 16 12:19:36 2009 -0400
@@ -324,11 +324,12 @@
matcher.sub(src2_name, flag_code),
matcher.sub(src2_name, cond_check),
matcher.sub(src2_name, else_code))
+ imm_name = "%simm8" % match.group("prefix")
self.buildCppClasses(name + "i", Name, suffix + "Imm",
- matcher.sub("imm8", code),
- matcher.sub("imm8", flag_code),
- matcher.sub("imm8", cond_check),
- matcher.sub("imm8", else_code))
+ matcher.sub(imm_name, code),
+ matcher.sub(imm_name, flag_code),
+ matcher.sub(imm_name, cond_check),
+ matcher.sub(imm_name, else_code))
return
# If there's something optional to do with flags, generate
@@ -353,13 +354,16 @@
matcher = re.compile("(?<!\w)spsrc2(?!\w)")
if matcher.search(allCode):
code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" +
code
+ matcher = re.compile("(?<!\w)simm8(?!\w)")
+ if matcher.search(allCode):
+ code = "int16_t simm8 = (int16_t)((int8_t)imm8);" + code
base = "X86ISA::RegOp"
# If imm8 shows up in the code, use the immediate templates, if
# not, hopefully the register ones will be correct.
templates = regTemplates
- matcher = re.compile("(?<!\w)imm8(?!\w)")
+ matcher = re.compile("(?<!\w)s?imm8(?!\w)")
if matcher.search(allCode):
base += "Imm"
templates = immTemplates
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