[m5-dev] [PATCH 19 of 20] inorder: enforce stage bandwidth

[Korey Sewell]

# HG changeset patch
# User Korey Sewell <ksew...@umich.edu>
# Date 1254427253 14400
# Node ID 40f8c3d3f08c9cc6c27922ff9fd3a30f8b2b788b
# Parent  0760590f19d8517feb0bcc3f8d78f4cb1b57b1cd
inorder: enforce stage bandwidth
each stage keeps track of insts_processed on a per_thread basis but we should
be keeping that on a total basis inorder to enforce stage width limits

diff --git a/src/cpu/inorder/first_stage.cc b/src/cpu/inorder/first_stage.cc
--- a/src/cpu/inorder/first_stage.cc
+++ b/src/cpu/inorder/first_stage.cc
@@ -182,6 +182,7 @@
 
         // Don't let instruction pass to next stage if it hasnt completed
         // all of it's requests for this stage.
+        instsProcessed++;        
         all_reqs_completed = processInstSchedule(inst);
 
         if (!all_reqs_completed) {
diff --git a/src/cpu/inorder/pipeline_stage.cc 
b/src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -709,8 +709,10 @@
         nextStage->size = 0;
 
     toNextStageIndex = 0;
+    
+    sortInsts();
 
-    sortInsts();
+    instsProcessed = 0;
 
     processStage(status_change);
 
@@ -856,10 +858,8 @@
     DynInstPtr inst;
     bool last_req_completed = true;
 
-    int insts_processed = 0;
-
     while (insts_available > 0 &&
-           insts_processed < stageWidth &&
+           instsProcessed < stageWidth &&
            (!nextStageValid || canSendInstToStage(stageNum+1)) &&
            last_req_completed) {
         assert(!insts_to_stage.empty());
@@ -884,6 +884,9 @@
             continue;
         }
 
+        // If the instruction isnt squashed, then we can officially count
+        // this instruction toward the stage's bandwidth count
+        instsProcessed++;
 
         last_req_completed = processInstSchedule(inst);
 
@@ -899,8 +902,6 @@
             break;
         }
 
-        insts_processed++;
-
         insts_to_stage.pop();
 
         //++stageProcessedInsts;
diff --git a/src/cpu/inorder/pipeline_stage.hh 
b/src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -270,6 +270,9 @@
     std::vector<DynInstPtr> switchedOutBuffer;
     std::vector<bool> switchedOutValid;
 
+    /** Instructions that we've tried to processed this tick (reset every 
cycle) */
+    unsigned instsProcessed;    
+
     /** Queue of all instructions coming from previous stage on this cycle. */
     std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
 
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