# HG changeset patch
# User Korey Sewell <[email protected]>
# Date 1254427253 14400
# Node ID 1b1e68dddbf3133a837dec1f3dcd736ec67a89ce
# Parent 40f8c3d3f08c9cc6c27922ff9fd3a30f8b2b788b
inorder: pipeline stage stats
add idle/run/utilization stats for each pipeline stage
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -328,7 +328,12 @@
{
/* Register the Resource Pool's stats here.*/
resPool->regStats();
-
+
+ /* Register for each Pipeline Stage */
+ for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
+ pipelineStage[stage_num]->regStats();
+ }
+
/* Register any of the InOrderCPU's stats here.*/
timesIdled
.name(name() + ".timesIdled")
@@ -1272,8 +1277,14 @@
DPRINTF(Activity, "Waking up CPU\n");
- //@todo: figure out how to count idleCycles correctly
- //idleCycles += (curTick - 1) - lastRunningCycle;
+ Tick extra_cycles = tickToCycles((curTick - 1) - lastRunningCycle);
+
+ idleCycles += extra_cycles;
+ for (int stage_num = 0; stage_num < NumStages; stage_num++) {
+ pipelineStage[stage_num]->idleCycles += extra_cycles;
+ }
+
+ numCycles += extra_cycles;
mainEventQueue.schedule(&tickEvent, curTick);
}
diff --git a/src/cpu/inorder/first_stage.cc b/src/cpu/inorder/first_stage.cc
--- a/src/cpu/inorder/first_stage.cc
+++ b/src/cpu/inorder/first_stage.cc
@@ -128,6 +128,13 @@
DPRINTF(InOrderStage, "No more threads to fetch from.\n");
}
}
+
+ if (instsProcessed > 0) {
+ ++runCycles;
+ } else {
+ ++idleCycles;
+ }
+
}
//@TODO: Note in documentation, that when you make a pipeline stage change,
then
@@ -137,7 +144,9 @@
{
bool all_reqs_completed = true;
- for (int insts_fetched = 0; insts_fetched < stageWidth &&
canSendInstToStage(1); insts_fetched++) {
+ for (int insts_fetched = 0;
+ insts_fetched < stageWidth && canSendInstToStage(1);
+ insts_fetched++) {
DynInstPtr inst;
bool new_inst = false;
@@ -198,7 +207,6 @@
}
sendInstToNextStage(inst);
- //++stageProcessedInsts;
}
// Record that stage has written to the time buffer for activity
diff --git a/src/cpu/inorder/pipeline_stage.cc
b/src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -71,41 +71,27 @@
std::string
PipelineStage::name() const
{
- return cpu->name() + ".stage-" + to_string(stageNum);
+ return cpu->name() + ".stage-" + to_string(stageNum);
}
void
PipelineStage::regStats()
{
-/* stageIdleCycles
- .name(name() + ".IdleCycles")
- .desc("Number of cycles stage is idle")
- .prereq(stageIdleCycles);
- stageBlockedCycles
- .name(name() + ".BlockedCycles")
- .desc("Number of cycles stage is blocked")
- .prereq(stageBlockedCycles);
- stageRunCycles
- .name(name() + ".RunCycles")
- .desc("Number of cycles stage is running")
- .prereq(stageRunCycles);
- stageUnblockCycles
- .name(name() + ".UnblockCycles")
- .desc("Number of cycles stage is unblocking")
- .prereq(stageUnblockCycles);
- stageSquashCycles
- .name(name() + ".SquashCycles")
- .desc("Number of cycles stage is squashing")
- .prereq(stageSquashCycles);
- stageProcessedInsts
- .name(name() + ".ProcessedInsts")
- .desc("Number of instructions handled by stage")
- .prereq(stageProcessedInsts);
- stageSquashedInsts
- .name(name() + ".SquashedInsts")
- .desc("Number of squashed instructions handled by stage")
- .prereq(stageSquashedInsts);*/
+ idleCycles
+ .name(name() + ".idleCycles")
+ .desc("Number of cycles 0 instructions are processed.");
+
+ runCycles
+ .name(name() + ".runCycles")
+ .desc("Number of cycles 1+ instructions are processed.");
+
+ utilization
+ .name(name() + ".utilization")
+ .desc("Percentage of cycles stage was utilized (processing insts).")
+ .precision(6);
+ utilization = (runCycles / cpu->numCycles) * 100;
+
}
@@ -786,6 +772,12 @@
nextStage->size, stageNum + 1);
}
+ if (instsProcessed > 0) {
+ ++runCycles;
+ } else {
+ ++idleCycles;
+ }
+
DPRINTF(InOrderStage, "%i left in stage %i incoming buffer.\n", skidSize(),
stageNum);
@@ -803,12 +795,6 @@
// continue trying to empty skid buffer
// check if stall conditions have passed
- if (stageStatus[tid] == Blocked) {
- ;//++stageBlockedCycles;
- } else if (stageStatus[tid] == Squashing) {
- ;//++stageSquashCycles;
- }
-
// Stage should try to process as many instructions as its bandwidth
// will allow, as long as it is not currently blocked.
if (stageStatus[tid] == Running ||
@@ -850,8 +836,6 @@
if (insts_available == 0) {
DPRINTF(InOrderStage, "[tid:%u]: Nothing to do, breaking out"
" early.\n",tid);
- // Should I change the status to idle?
- //++stageIdleCycles;
return;
}
@@ -875,8 +859,6 @@
"squashed, skipping.\n",
tid, inst->seqNum, inst->readPC());
- //++stageSquashedInsts;
-
insts_to_stage.pop();
--insts_available;
@@ -904,7 +886,6 @@
insts_to_stage.pop();
- //++stageProcessedInsts;
--insts_available;
}
diff --git a/src/cpu/inorder/pipeline_stage.hh
b/src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -349,24 +349,19 @@
std::vector<ResReqPtr> resources;
};
- /** Tracks which stages are telling decode to stall. */
+ /** Tracks stage/resource stalls */
Stalls stalls[ThePipeline::MaxThreads];
- //@TODO: Use Stats for the pipeline stages
- /** Stat for total number of idle cycles. */
- //Stats::Scalar stageIdleCycles;
- /** Stat for total number of blocked cycles. */
- //Stats::Scalar stageBlockedCycles;
- /** Stat for total number of normal running cycles. */
- //Stats::Scalar stageRunCycles;
- /** Stat for total number of unblocking cycles. */
- //Stats::Scalar stageUnblockCycles;
- /** Stat for total number of squashing cycles. */
- //Stats::Scalar stageSquashCycles;
- /** Stat for total number of staged instructions. */
- //Stats::Scalar stageProcessedInsts;
- /** Stat for total number of squashed instructions. */
- //Stats::Scalar stageSquashedInsts;
+ /** Number of cycles 0 instruction(s) are processed. */
+ Stats::Scalar idleCycles;
+
+ /** Number of cycles instruction(s) are processed. */
+ Stats::Scalar runCycles;
+
+ /** Number of cycles instruction(s) are processed. */
+ Stats::Formula utilization;
+
+
};
#endif
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