Timothy M Jones wrote: > On Thu, 22 Oct 2009 09:36:49 +0100, Gabe Black <[email protected]> > wrote: > >> If you'd be willing, >> making it into a timing translation while you're allowing split accesses >> would be helpful for x86 in the future. > > I've made an initial patch by copying some of the code from > TimingSimpleCPU and have attached it here. Is this the kind of thing > we're looking for? > > As an aside, is there a reason why this translation is performed > within the dynamic instruction class and not, say, in the load/store > queue? > > Cheers > Tim > ------------------------------------------------------------------------ > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev >
Sorry for taking a while to get back to you. The translation used to be instant, so it was probably not really important where it happened. It looks like you're on the right track. O3 can be tricky to get right, so it might be a bigger change than what you have here in the end. One thing that might (but not necessarily) cause problems is that you're not immediately either forwarding the access to the CPU or faulting. O3 might make assumptions about that and not work that way sometimes, so you might have to fix that. Also, one petty request would be to make the author on tralsation.hh me and not Steve Reinhardt. He wrote the majority of the simple CPU, but I did the current version of translation. Keep us posted! Gabe _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
