If you'd be willing, making it into a timing translation while you're allowing split accesses would be helpful for x86 in the future.
I've made an initial patch by copying some of the code from TimingSimpleCPU and have attached it here. Is this the kind of thing we're looking for?
As an aside, is there a reason why this translation is performed within the dynamic instruction class and not, say, in the load/store queue?
Cheers Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336.
timing-translation.patch
Description: Binary data
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