Quoting Timothy M Jones <[email protected]>: > Thanks Gabe. > > I've run all regressions and there are some that fail. I've checked the > differences and it's mainly changes in the number of DTB accesses (as > expected). In some cases there are more Dcache accesses too (also > expected if speculative I guess). In general though, the number of ticks > stays exactly the same.
Why is that expected? Aren't you replacing one body of code with a functionally identical body that's just organized differently? I can imagine new functionality making certain benchmarks behave differently, but for all the (relatively) stable ISAs, what accesses are done, which ones are split, etc. should be pretty much the same. This is, of course, assuming that there isn't some other change mixed in there I'm forgetting about. Gabe _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
