On Wed, 02 Dec 2009 15:33:27 -0000, Steve Reinhardt <[email protected]> wrote:
> On Wed, Dec 2, 2009 at 2:01 AM, Timothy M Jones <[email protected]> > wrote: >> Well, the problem is when you get speculative memory accesses. Even in >> the ISAs that don't need split loads and stores, an address on a >> speculative path can generated that requires splitting. Of course, >> these >> instructions are later squashed, but their DTB and Dcache accesses might >> have already been performed, leading to more accesses than in the >> reference stats. > > I'd think that even without limiting splits to specific ISAs, these > cases should be handled like we just saw in PowerPC: that they would > trigger alignment faults before reaching the DTB or Dcache, and then > those alignment faults would get suppressed when the instructions were > found to be speculative. Is there a reason this isn't happening this > way? > The problem is that they might be aligned after splitting. Imagine a speculative double word read that is aligned on a word (but not double word) boundary. Usually this would trigger an alignment fault. However, in the current setup they are split and now we have two word accesses that are both aligned on word boundaries. Therefore these don't cause alignment faults and access the DTB and Dcache in the normal way. I'm going to implement your suggestion of having a const variable for each ISA that defines whether splitting is required or not. Then this problem will go away. However, if you like I can get a concrete example of when this happens under the current set of patches? Tim -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
