On Wed, Dec 2, 2009 at 2:01 AM, Timothy M Jones <[email protected]> wrote: > Well, the problem is when you get speculative memory accesses. Even in > the ISAs that don't need split loads and stores, an address on a > speculative path can generated that requires splitting. Of course, these > instructions are later squashed, but their DTB and Dcache accesses might > have already been performed, leading to more accesses than in the > reference stats.
I'd think that even without limiting splits to specific ISAs, these cases should be handled like we just saw in PowerPC: that they would trigger alignment faults before reaching the DTB or Dcache, and then those alignment faults would get suppressed when the instructions were found to be speculative. Is there a reason this isn't happening this way? Steve _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
