> > I haven't checked too carefully, but this same problem may be > affecting ARM as well (since I think it uses the same paired > floating-point register scheme). Also, other double-precision things > like checking for NaNs may be broken by this change. > Yea, I know I have got a few of the regressions for SPEC2K-INT on MIPS working, but was unable to fully get working twolf as I think that particular benchmark wants to use some floating point as well...
As you note earlier, M5 used to handle this correctly but it was a bit tricky in implementation. Because the bits need to be concatenated together for double precision you cant keep that floating point register file as an array of "FloatReg" since the bits will be out of order for concatenation. Instead, you need to keep each register really as a "IntReg" or "uint32_t", then when you want to read a floating point reg you have to do some manipulation to read it out for the right floating type and width. So in concept a "FloatReg f" register file wont work correctly here. I had it all working before so maybe a simple peek to the old code can be used to update the new code if need be. Also, for MIPS since there are 32-bit and 64-bit precision, there should be two types available to distinguish things "FloatReg32" and "FloatReg64". -- - Korey
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